Manchester decoder - Signal Pro

1 _____Signal Processing Group Inc., technical memorandum, July 2013. SPG designs, develops and manufactures highly costeffective analog and RF/wireless ASICs and modules using state of the artsemiconductor, PCB and assembly technologies. Please contact us from ourwebsite for fast, effective and friendly decoderManchester CodeManchester code embeds clock information with data in avery simple way:each bit is transmitted with a transition inthe middle ofthebit time. For a 0 , transition is 0 to 1, for a 1 ,transition is 1 to 0 (Figure 1).Figure below illustrates a Manchester encoded bit idea is to have multiple transitions in the stream even for long sequencesof 1 and 0 data. This enables the Manchester data stream to carry theclock as well as thedata. The data and clock can be extracted by amanchester decoder , the subject of this brief principle of the decoder presented in this , from Figure above, thatthe bitvalue is present during the firsthalf of bit time, before theFigure Manchester encoding protocolFigure Multiple bits in Manchester format_____Signal Processing Group Inc.

2 , technical memorandum, July 2013. SPG designs, develops and manufactures highly costeffective analog and RF/wireless ASICs and modules using state of the artsemiconductor, PCB and assembly technologies. Please contact us from ourwebsite for fast, effective and friendly edge. If a delay ofthree-fourths bit time istriggered by theincoming mid-bit transition, the value captured at the end of the delay willindicate the next bit value. Please see Figure the next bit value is 1 , the receiver sets a Signal to invert theinput bit stream polarity, so the next Signal transition appears as alow-to-high transition (Figure 4). If the next bit value is 0 , thereceiverresets the inverted figure belowshows this operation TFigure Principle of the decoder0110 T T110 Sampling instants_____Signal Processing Group Inc.

3 , technical memorandum, July 2013. SPG designs, develops and manufactures highly costeffective analog and RF/wireless ASICs and modules using state of the artsemiconductor, PCB and assembly technologies. Please contact us from ourwebsite for fast, effective and friendly Principle of the receiverSerialmanchesterdata T0110 T T110 Sampling instantsPolarityinvertinputPolarityinver tXOR serialdatain(Decoded data)(Serial recovered clock)_____Signal Processing Group Inc., technical memorandum, July 2013. SPG designs, develops and manufactures highly costeffective analog and RF/wireless ASICs and modules using state of the artsemiconductor, PCB and assembly technologies. Please contact us from ourwebsite for fast, effective and friendly fundamental operation is embodied in the schematic shown belowA16X bit rate clock is used.

4 A 4 bit counter follows the clock. A decodingcircuit is used at theoutput of the counter to generate a period delay( DEL12). The positive edge of this Signal is used as the clock input of thefollowingDFF. Each time this positive edge occurs the value ( 1 or 0) at theD input of the FF is output of this FF is connected to one input of the XOR gate. The otherinput of the XOR is connected to the serial data input. The falling edge ofthe XOR starts the operation by allowing the clock to be gated to thecounter. The DEL12 output resets the operation automatically. An externalFigure 5: The receiver_____Signal Processing Group Inc., technical memorandum, July 2013. SPG designs, develops and manufactures highly costeffective analog and RF/wireless ASICs and modules using state of the artsemiconductor, PCB and assembly technologies.

5 Please contact us from ourwebsite for fast, effective and friendly reset is provided at the Reset input also, that sets all the variables totheir initial states for correct this schematic as a reference and the description of the decoderpresented above it should be clear that this circuit implements the questions or comments should be referred to the author via