KSZ8041TL/FTL/MLL Data Sheet - Microchip …

1 2017 Microchip Technology Inc. DS00002436B-page 1 Features Single-Chip 10 BASE-T/100 BASE-TX/100 BASE-FX Physical Layer Solution Fully Compliant with IEEE Standard Low Power CMOS Design, Power Consumption of <180 mW HP Auto MDI/MDI-X for Reliable Detection and Correction for Straight-Through and Crossover Cables with Disable and Enable Option Robust Operation Over Standard Cables LinkMD TDR-Based Cable Diagnostics for Iden-tification of Faulty Copper Cabling Power Down and Power Saving Modes Fiber Support: 100 BASE-FX (KSZ8041 FTL Only) Back-to-Back Mode Support for 100 Mbps Repeater or Media Converter MII Interface Support RMII Interface Support with External 50 MHz Sys-tem Clock (KSZ8041TL/FTL Only) SMII Interface Support with External 125 MHz System Clock and MHz Sync Clock from MAC (KSZ8041TL/FTL Only) MIIM (MDC/MDIO) Management Bus to MHz for Rapid PHY Register Configuration Interrupt Pin Option Programmable LED Outputs for Link, Activity, and Speed Single Power Supply ( ) Built-in Regulator for Core Available in 48-Pin LQFP (KSZ8041 MLL) or 48-Pin TQFP (KSZ8041TL/FTL)

2 PackagesApplications Printer LOM Game Console IPTV IP Phone IP Set-Top Box Media ConverterKSZ8041TL/FTL/MLL10 BASE-T/100 BASE-TX/100 BASE-FXPhysical Layer TransceiverKSZ8041TL/FTL/MLLDS00002436B- page 2 2017 Microchip Technology OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at We welcome your Current Data SheetTo obtain the most up-to-date version of this data Sheet , please register at our Worldwide Web site at: can determine the version of a data Sheet by examining its literature number found on the bottom outside corner of any page.

3 The last character of the literature number is the version number, ( , DS30000000A is version A of document DS30000000).ErrataAn errata Sheet , describing minor operational differences from the data Sheet and recommended workarounds, may exist for cur-rent devices. As device/documentation issues become known to us, we will publish an errata Sheet . The errata will specify therevision of silicon and revision of document to which it determine if an errata Sheet exists for a particular device, please check with one of the following: Microchip s Worldwide Web site; Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data Sheet (include -literature number) you Notification SystemRegister on our web site at to receive the most current information on all of our products.

4 2017 Microchip Technology Inc. DS00002436B-page 3 KSZ8041TL/FTL/MLLT able of Introduction .. Pin Description and Configuration .. Functional Description .. Register Descriptions .. Operational Characteristics .. Electrical Characteristics .. Timing Specifications .. Selection of Isolation Transformers .. Package Outline .. 57 Appendix A: Data Sheet Revision History .. 59 The Microchip Web Site .. 60 Customer Change Notification Service .. 60 Customer Support .. 60 Product Identification System .. 61 KSZ8041TL/FTL/MLLDS00002436B-page 4 2017 Microchip Technology DescriptionThe KSZ8041TL is a single supply 10 BASE-T/100 BASE-TX Physical Layer Transceiver that provides MII/RMII/SMII interfaces to transmit and receive data.

5 It utilizes a unique mixed-signal design to extend signaling distance while reduc-ing power Auto MDI/MDI-X provides the most robust solution for eliminating the need to differentiate between crossover andstraight-through TDR-based cable diagnostics permit identification of faulty copper KSZ8041TL represents a new level of features and performance and is an ideal choice of physical layer transceiverfor 10 BASE-T/100 BASE-TX KSZ8041 FTL has all the identical rich features of the KSZ8041TL plus 100 BASE-FX support for fiber and mediaconverter KSZ8041 MLL is the basic 10 BASE-T/100 BASE-TX physical layer transceiver version with MII KSZ8041TL and KSZ8041 FTL are available in 48-pin, lead-free TQFP packages. The KSZ8041 MLL is provided inthe 48-pin, lead-free LQFP 1-1:SYSTEM BLOCK DIAGRAM, KSZ8041TL/FTL 10/100 PulseShaperNRZ/NRZIMLT3 EncoderParallel /SerialManchester Encoder4B/5B EncoderScramblerParallel /SerialTransmitterTX+TX-Adaptive EQBase LineWander CorrectionMLT3 DecoderNRZI/NRZC lockRecovery4B/5B DecoderDescramblerSerial /ParallelAutoNegotiation10 BASE-TReceiverManchester DecoderSerial /ParallelPLLLEDD riverMII/RMII/SMIIR egistersandControllerInterfaceRX-RX+XIXO LED1 LED0 Power DownPower SavingTXD3 TXD0 TXD1 TXD2 RXD3 TXENTXCMDCMDIORXERRXD0 RXD1 RXD2 REXTRXCRXDVCRSCOLRST#INTRP100 BASE-FXSignal Detect(KSZ8041 FTL Only)FXSD/FXEN 2017 Microchip Technology Inc.

6 DS00002436B-page 5 KSZ8041TL/FTL/MLLFIGURE 1-2:SYSTEM BLOCK DIAGRAM, KSZ8041 MLL 10/100 PulseShaperNRZ/NRZIMLT3 EncoderParallel /SerialManchester Encoder4B/5B EncoderScramblerParallel /SerialTransmitterTX+TX-Adaptive EQBase LineWander CorrectionMLT3 DecoderNRZI/NRZC lockRecovery4B/5B DecoderDescramblerSerial /ParallelAutoNegotiation10 BASE-TReceiverManchester DecoderSerial /ParallelPLLLEDD riverMIIRX-RX+XIXOLED1 LED0 Power DownPower SavingTXD3 TXD0 TXD1 TXD2 RXD3 TXENTXCMDCMDIORXERRXD0 RXD1 RXD2 REXTRXCRXDVCRSCOLRST#INTRPKSZ8041TL/FTL/ MLLDS00002436B-page 6 2017 Microchip Technology DESCRIPTION AND CONFIGURATIONFIGURE 2-1:KSZ8041TL 48-PIN TQFP ASSIGNMENT, (TOP VIEW)1 NCNCTXCRST#INTRPREXTGNDRXER / RX_ER / TXD[1] / SYNCTXD0 / TXD[0] / TXTXEN /TX_ENLED1 /SPEEDLED0 /NWAYENCRS /CONFIG1NC238131416172930313233343536414 2434445464748RX+TX-RX-91011 GND24 TXD3 TXD2 GNDCOL / CRSDV /CONFIG225262728 RXD2 / PHYAD1 RXD1 / RXD[1] / PHYAD2 RXD0 / RXD[0] / RXDUPLEX212223 MDIOMDCRXD3 / PHYAD0181920XI / REFCLK / CLOCK15TX+ 2017 Microchip Technology Inc.

7 DS00002436B-page 7 KSZ8041TL/FTL/MLLFIGURE 2-2:KSZ8041 FTL 48-PIN TQFP ASSIGNMENT, (TOP VIEW)1 NCNCTXCRST#INTRPREXTGNDRXER / RX_ER /FXENTXD1 / TXD[1] / SYNCTXD0 / TXD[0] / TXTXEN /TX_ENLED1 /SPEED / no FEFLED0 /NWAYENCRS /CONFIG1NC238131416172930313233343536414 2434445464748RX+TX-RX-91011 GND24 TXD3 TXD2 GNDCOL / CRSDV /CONFIG225262728 RXD2 / PHYAD1 RXD1 / RXD[1] / PHYAD2 RXD0 / RXD[0] / RXDUPLEX212223 MDIOMDCRXD3 / PHYAD0181920XI / REFCLK / CLOCK15TX+ KSZ8041TL/FTL/MLLDS00002436B-page 8 2017 Microchip Technology 2-1:SIGNALS FOR KSZ8041TL/FTLPin NumberPin NameType (Note2-1) analog analog output voltage from analog analog VDD9RX I/OPhysical receive or transmit signal ( differential)10RX+I/OPhysical receive or transmit signal (+ differential)11TX I/OPhysical transmit or receive signal ( differential)12TX+I/OPhysical transmit or receive signal (+ differential)13 GNDGNDG round14 XOOC rystal feedbackThis pin is used only in MII mode when a 25 MHz crystal is pin is a no connect if oscillator or external clock source is used, or if RMII mode or SMII mode is Clock InputMII Mode: 25 MHz 50 ppm (crystal, oscillator, or external clock)RMII Mode: 50 MHz 50 ppm (oscillator, or external clock only)SMII Mode.

8 125 MHz 100 ppm (oscillator, or external clock only)16 REXTI/OSet physical transmit output currentConnect a k resistor in parallel with a 100 pF capacitor to ground on this pin. See KSZ8041TL-FTL reference Interface (MII) Data I/OThis pin requires an external k pull-up Interface (MII) Clock InputThis pin is synchronous to the MDIO data Mode: Receive Data Output[3](Note 2-2) Config. Mode: The pull-up/pull-down value is latched as PHYADDR[0] during power-up/reset. See Table 2-2 for Mode: Receive Data Output[2](Note 2-2) Config. Mode: The pull-up/pull-down value is latched as PHYADDR[1] during power-up/reset. See Table 2-2 for details. 2017 Microchip Technology Inc. DS00002436B-page 9 KSZ8041TL/FTL/MLL22 RXD1/RXD[1]/PHYAD2 Ipd/OMII Mode: Receive Data Output[1](Note 2-2) RMII Mode: Receive Data Output[1](Note 2-3) Config.

9 Mode: The pull-up/pull-down value is latched as PHYADDR[2] during power-up/reset. See Table 2-2 for [0]/RXDUPLEXIpu/OMII Mode: Receive Data Output[0](Note 2-2) RMII Mode: Receive Data Output[0](Note 2-3) SMII Mode: Receive Data and Control(Note 2-4) Config. Mode: Latched as DUPLEX (register 0h, bit 8) during power-up/reset. See Ta b l e 2 - 2 for digital digital VDD27 RXDV/CRSDV/CONFIG2 Ipd/OMII Mode: Receive Data Valid Output RMII Mode: Carrier Sense/Receive Data Valid Output Config. Mode: The pull-up/pull-down value is latched as CONFIG2 during power-up/reset. See Table 2-2 for Mode: Receive Clock Mode: Receive Error Output RMII Mode: Receive Error Output Config. Mode: The pull-up/pull-down value is latched as ISOLATE during power-up/reset.

10 See Table 2-2 for digital VDD32 INTRPOpuInterrupt Output: Programmable Interrupt OutputRegister 1Bh is the Interrupt Control/Status Register for programming the interrupt conditions and reading the interrupt status. Register 1Fh bit 9 sets the interrupt output to active-low (default) or Mode: Transmit Clock OutputMII Back-to-Back Mode: Transmit Clock Input34 TXEN/TX_ENIMII Mode: Transmit Enable Input RMII Mode: Transmit Enable Input35 TXD0/TXD[0]/TXIMII Mode: Transmit Data Input[0](Note 2-5) RMII Mode: Transmit Data Input[0](Note 2-6) SMII Mode: Transmit Data and Control(Note 2-7)36 TXD1/TXD[1]/SYNCIMII Mode: Transmit Data Input[1](Note 2-5) RMII Mode: Transmit Data Input[1](Note 2-6) SMII Mode: SYNC Clock Input37 GNDGNDG round38 TXD2 IMII Mode: Transmit Data Input[2](Note 2-5) 39 TXD3 IMII Mode: Transmit Data Input[3](Note 2-5) TABLE 2-1.