Memory in SystemVerilog

1 Memory in SystemVerilogProf. Stephen A. EdwardsColumbia UniversitySpring 2015 Implementing MemoryMemory = Storage Element Array + AddressingBits are expensiveThey should dumb, cheap, small, and tighly packedBits are numerousCan t just connect a long wire to each oneWilliams TubeCRT-based random access Memory , 1946. Used on theManchester Mark I. 2048 acoustic delay lineUsed in the EDASC, 17 bitsSelectron TubeRCA, 128 bitsFour-dimensional addressingA four-input AND gate ateach bit for selectionMagnetic CoreIBM, Drum Memory1950s & 60s. Secondary Memory ChoicesFamilyProgrammedPersistenceMask ROMat fabrication PROM once EPROM1000s, UV10 yearsFLASH1000s, block10 yearsEEPROM1000s, byte10 yearsNVRAM 5 yearsSRAM while poweredDRAM 64 msImplementing ROMs0/10Z: notconnected 010111 Add. Data000110111010100110102-to-4 DecoderA1A0011110100010 Wordline 00 Wordline 11 Wordline 22 Wordline 33 Bitline 0D0 Bitline 1D1 Bitline 2D2 Implementing ROMs0/10Z: notconnected 010111 Add.

2 Data000110111010100110102-to-4 Decoder1A10A0011110100010 Wordline 00 Wordline 11 Wordline 22 Wordline 33 Bitline 0D0 Bitline 1D1 Bitline 2D21000010 Implementing ROMs0/10Z: notconnected 010111 Add. Data000110111010100110102-to-4 DecoderA1A00123D0D1D2 Implementing ROMs0/10Z: notconnected 010111 Add. Data000110111010100110102-to-4 DecoderA1A00123D0D1D20011101 Mask ROM Die PhotoA Floating Gate MOSFETC ross section of a NOR FLASH transistor. Kawai et al., ISSCC 2008 (Renesas)Floating Gate n-channel MOSFETC hannelDrainSourceFloating GateControl GateSiO2 Floating gate uncharged; Control gate at 0V: OffFloating Gate n-channel MOSFETC hannelDrainSourceFloating GateControl GateSiO2+++++++++ +++++++++ Floating gate uncharged; Control gate positive: OnFloating Gate n-channel MOSFETC hannelDrainSourceFloating GateControl GateSiO2 ++++++++Floating gate negative; Control gate at 0V: OffFloating Gate n-channel MOSFETC hannelDrainSourceFloating GateControl GateSiO2++++++++ ++Floating gate negative; Control gate positive: OffEPROMs and FLASH use Floating-Gate MOSFETsStatic Random-Access Memory CellWord lineBit lineBit lineLayout of a 6T SRAM Cell !

3 ! $% $% &$'() "# Weste and to cmos vlsi Design. Addison-Wesley, s 2102 SRAM, 1024 1 bit, 19722102 Block DiagramSRAM 8 SRAMCS1CS2 WEOEAddr12 Datawrite 1read 26264 SRAM Block DiagramCY6264-1A1A2A3A4A5A6A7A8I/O0256 x 32 x 8 ARRAYINPUT BUFFERCOLUMN DECODERPOWERDOWNI/O1I/O2I/O3I/O4I/O5I/O6 I/O7CE1CE2 WEOET oshiba TC55V16256J 256K 16 SRAMD ynamic RAM CellRowColumnAncient (c. 1982) DRAM: 4164 64K 1 DRAMB asic DRAM read and write cyclesRASCASAddrRowColRowColWEDinto writeDoutreadPage Mode DRAM read cycleRASCASAddrRowColColColWEDinDoutread readreadSamsung 8M 16 16 SDRAMBank SelectData Input Register8M x 4 / 4M x 8 / 2M x 168M x 4 / 4M x 8 / 2M x 16 Sense AMPO utput BufferI/O ControlColumn DecoderLatency & Burst LengthProgramming RegisterAddress RegisterRow BufferRefresh CounterRow DecoderCol. BufferLRASLCBRLCKELRASLCBRLWELDQMCLKCKEC SRASCASWEL(U)DQMLWELDQMDQiCLKADDLCASLWCB R8M x 4 / 4M x 8 / 2M x 168M x 4 / 4M x 8 / 2M x 16 Timing RegisterSDRAM: Control SignalsRASCASWE Action111 NOP000 Load mode register011 Active (select row)101 Read (select column, start burst)100 Write (select column, start burst)110 Terminate Burst010 Precharge (deselect row)001 Auto RefreshMode register: selects 1/2/4/8-word bursts, CAS latency,burst on writeSDRAM.

4 Timing with 2-word burstsClkRASCASWEAddrOpRCCBABBBDQWWRRLoa dActiveWriteReadRefreshUsing Memory inSystemVerilogBasic Memory ModelAddressData InWriteClockData OutMemoryClockAddressA0A1A1 Data InD1 WriteData OutD0old D1D1 Read A0 Basic Memory ModelAddressData InWriteClockData OutMemoryClockAddressA0A1A1 Data InD1 WriteData OutD0old D1D1 Write A1 Basic Memory ModelAddressData InWriteClockData OutMemoryClockAddressA0A1A1 Data InD1 WriteData OutD0old D1D1 Read A1 Memory Is Fundamentally a BottleneckPlenty of bits, butYou can only see a small window eachclock cycleUsing Memory = scheduling memoryaccessesSoftware hides this from you: sequentialprograms naturally schedule accessesYou must schedule Memory accesses in ahardware designModeling Synchronous Memory in SystemVerilogmodulememory(input logicclk ,input logicwriteWrite enablewrite ,input logic[3:0]address4-bit addressaddress ,input logic[7:0]data_in8-bit input busdata_in ,output logic[7:0]data_out8-bit output busdata_out);logic[7:0]memThe Memory array: 16 8-bit bytesmem [15:0];always_ff@(posedge clkClockedposedge clk)beginif(write)mem[address] <=data_inWrite to array when askeddata_in;data_out <=mem[address]Always read (old) value from arraymem[address].

5 EndendmoduleM10K Blocks in the Cyclone V10 kilobits (10240 bits) per blockDual ported: two addresses, write enable signalsData busses can be 1 20 bits wideOur Cyclone V 5 CSXFC6 has 557 of these blocks (696 KB) Memory in Quartus: the Megafunction WizardMemory: Single- or Dual-PortedMemory: Select Port WidthsMemory: One or Two ClocksMemory: Output Ports Need Not Be RegisteredMemory: Wizard-Generated Verilog ModuleThis generates the following SystemVerilog module:modulememory (// Port A:input logic[12:0] address_a,// 8192 1-bit wordsinput logicclock_a,input logic[0:0] data_a,input logicwren_a,// Write enableoutput logic[0:0] q_a,// Port B:input logic[8:0] address_b,// 512 16-bit wordsinput logicclock_b,input logic[15:0] data_b,input logicwren_b,// Write enableoutput logic[15:0] q_b);Instantiate like any module; Quartus treats speciallyTwo Ways to Ask for Memory1.

6 Use the Megafunction Wizard+Warns you in advance about resource usage Awkward to change2. Let Quartus infer Memory from your code+Better integrated with your code Easy to inadvertantly ask for garbageThe Perils of Memory Inferencemoduletwoport(input logicclk,input logic[8:0] aa, ab,input logic[19:0] da, db,input logicwa, wb,output logic[19:0] qa, qb);logic[19:0] mem [511:0];always_ff@(posedgeclk)beginif(wa ) mem[aa] <= da;qa <= mem[aa];if(wb) mem[ab] <= db;qb <= mem[ab];endendmoduleFailure: Exploded!Synthesized to an 854-pageschematic with 10280registers (no M10K blocks)Page 1 looked like this:The Perils of Memory Inferencemoduletwoport2(input logicclk,input logic[8:0] aa, ab,input logic[19:0] da, db,input logicwa, wb,output logic[19:0] qa, qb);logic[19:0] mem [511:0];always_ff@(posedgeclk)beginif(wa ) mem[aa] <= da;qa <= mem[aa];endalways_ff@(posedgeclk)beginif (wb) mem[ab] <= db;qb <= mem[ab];endendmoduleFailureStill didn t work:RAM logic mem isuninferred due tounsupportedread-during-write behaviorThe Perils of Memory Inferencemoduletwoport3(input logicclk,input logic[8:0] aa, ab,input logic[19:0] da, db,input logicwa, wb,output logic[19:0] qa, qb);logic[19:0] mem [511:0];always_ff@(posedgeclk)beginif(wa )beginmem[aa] <= da;qa <= da;end elseqa <= mem[aa];endalways_ff@(posedgeclk)beginif (wb)beginmem[ab] <= db;qb <= db.

7 End elseqb <= mem[ab];endendmoduleFinally!Took this structure from atemplate: Edit InsertTemplate Verilog HDL FullDesigns RAMs andROMs True Dual-Port RAM(single clock)clkqa[0]~reg[ ]DCLKQmemSYNC_RAMWECLK0 PORTBWEPORTBCLK0 DATAIN[ ]WADDR[ ]RADDR[ ]PORTBDATAIN[ ]PORTBWADDR[ ]PORTBRADDR[ ]PORTBDATAOUT[0]PORTBDATAOUT[1]PORTBDATA OUT[2]PORTBDATAOUT[3]PORTBDATAOUT[4]PORT BDATAOUT[5]PORTBDATAOUT[6]PORTBDATAOUT[7 ]PORTBDATAOUT[8]PORTBDATAOUT[9]PORTBDATA OUT[10]PORTBDATAOUT[11]PORTBDATAOUT[12]P ORTBDATAOUT[13]PORTBDATAOUT[14]PORTBDATA OUT[15]PORTBDATAOUT[16]PORTBDATAOUT[17]P ORTBDATAOUT[18]PORTBDATAOUT[19]DATAOUT[ ]qa[ ]qb[0]~reg[ ]DCLKQqb[ ]da[ ]db[ ]ab[ ]wbaa[ ]waThe Perils of Memory Inferencemoduletwoport4(input logicclk,input logic[8:0] ra, wa,input logicwrite,input logic[19:0] d,output logic[19:0] q);logic[19:0] mem [511:0];always_ff@(posedgeclk)beginif(wr ite) mem[wa] <= d.

8 Q <= mem[ra];endendmoduleAlso works: separate readand write addressesclkd[ ]q[ ]q[0]~reg[ ]DCLKQmemSYNC_RAMWECLK0 DATAIN[ ]WADDR[ ]RADDR[ ]DATAOUT[ ]ra[ ]wa[ ]writeConclusion:Inference is fine for singleport or one read and onewrite the Megafunction Wizardfor anything else.