Memory Testing and Built -In Self -Test

1 EE1411 VLSI Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 1 Chapter Chapter 88 Memory Testing and BuiltMemory Testing and Built --In SelfIn Self--TestTestEE1412 VLSI Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 2 What is this chapter about?What is this chapter about? Basic concepts of Memory Testing andBIST Memory fault models and test algorithms Memory fault simulation and test algorithm generation RAMSES: fault simulator TAGS: test algorithm generator Memory BIST BRAINS: BIST generatorEE1413 VLSI Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 3 Typical RAM Production FlowTypical RAM Production FlowWaferWaferFull Probe TestMarkingFinal TestShippingQA Sample TestVisual InspectionBurn-In (BI)Post-BI TestLaser RepairPackagingPre-BI TestEE1414 VLSI Test Principles and ArchitecturesCh.

2 8 - Memory Testing & BIST - P. 4 OffOff--Line Testing of RAMLine Testing of RAM Parametric Test: DC & AC Reliability Screening Long-cycle Testing Burn-in: static & dynamic BI Functional Test Device characterization Failure analysis Fault modeling Simple but effective (accurate & realistic?) Test algorithm generation Small number of test patterns (data backgrounds) High fault coverage Short test timeEE1415 VLSI Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 5 DRAM Functional ModelDRAM Functional ModelRead/write & chip enableAddress latchColumn decoderMemory cell arrayRow decoderRefresh logicWrite driverData registerSense amplifiersAddressRefreshData outData inData flowControl flowEE1416 VLSI Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 6 DRAM Functional Model ExampleDRAM Functional Model ExampleEE1417 VLSI Test Principles and ArchitecturesCh.

3 8 - Memory Testing & BIST - P. 7 Functional Fault ModelsFunctional Fault Models Classical fault models are not sufficient to represent all important failure modes in RAM. Sequential ATPG is not possible for RAM. Functional fault models are commonly used for memories: They define functional behavior of faulty memories. New fault models are being proposed to cover new defects and failures in modern memories: New process technologies New devicesEE1418 VLSI Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 8 Static RAM Fault Models: SAF/TFStatic RAM Fault Models: SAF/TF Stuck-At Fault (SAF) Cell (line) SA0 or SA1 A stuck-at fault (SAF) occurs when the value of a cell or line is always 0 (a stuck-at-0 fault) or always 1 (a stuck-at-1 fault). A test that detects all SAFs guarantees that from each cell, a 0 and a 1 must be read.

4 Transition Fault (TF) Cell fails to transit from 0 to 1 or 1 to 0 in specified time period. A cell has a transition fault (TF) if it fails to transit from 0to 1 (a < /0> TF) or from 1 to 0 (a < /1> TF).EE1419 VLSI Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 9 Static RAM Fault Models: AFStatic RAM Fault Models: AF Address-Decoder Fault (AF) An address decoder fault (AF) is a functional fault in the address decoder that results in one of four kinds of abnormal behavior: Given a certain address, no cell will be accessed A certain cell is never accessed by any address Given a certain address, multiple cells are accessed A certain cell can be accessed by multiple addressesEE14110 VLSI Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 10 Static RAM Fault Models: SOFS tatic RAM Fault Models: SOF Stuck-Open Fault (SOF) A stuck-open fault (SOF) occurs when the cell cannot be accessed due to, , a broken word line.

5 A read to this cell will produce the previously read Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 11 RAM Fault Models: CFRAM Fault Models: CF Coupling Fault (CF) A coupling fault (CF) between two cells occurs when the logic value of a cell is influenced by the content of, or operation on, another cell. State Coupling Fault (CFst) Coupled (victim) cell is forced to 0 or 1 if coupling (aggressor) cell is in given state. Inversion Coupling Fault (CFin) Transition in coupling cell complements (inverts) coupled cell. Idempotent Coupling Fault (CFid) Coupled cell is forced to 0 or 1 if coupling cell transits from 0 to 1 or 1 to Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 12 IntraIntra--Word & InterWord & Inter--Word CFsWord CFsEE14113 VLSI Test Principles and ArchitecturesCh.

6 8 - Memory Testing & BIST - P. 13 RAM Fault Models: DFRAM Fault Models: DF Disturb Fault (DF) Victim cell forced to 0 or 1 if we (successively) read or write aggressor cell (may be the same cell): Hammer test Read Disturb Fault (RDF) There is a read disturb fault (RDF) if the cell value will flip when being read (successively).EE14114 VLSI Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 14 RAM Fault Models: DRFRAM Fault Models: DRF Data Retention Fault (DRF) DRAM Refresh Fault Leakage Fault SRAM Leakage Fault Static Data Losses---defective pull-upEE14115 VLSI Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 15 Test Time Complexity Test Time Complexity (100 MHz)(100 MHz) Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 16 RAM Test AlgorithmRAM Test Algorithm A test algorithm (or simply test) is a finite sequence of test elements: A test element contains a number of Memory operations (access commands) Data pattern (background) specified for the Read and Write operation Address (sequence) specified for the Read and Write operations A march test algorithm is a finite sequence of march elements: A march element is specified by an address order and a finite number of Read/Write operationsEE14117 VLSI Test Principles and ArchitecturesCh.

7 8 - Memory Testing & BIST - P. 17 March Test NotationMarch Test Notation : address sequence is in the ascending order : address changes in the descending order : address sequence is either or r: the Read operation Reading an expected 0 from a cell (r0); reading an expected 1 from a cell (r1) w: the Write operation Writing a 0 into a cell (w0); writing a 1 into a cell (w1) Example (MATS+): )}0,1();1,0();0({wrwrw cEE14118 VLSI Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 18 Classical Test Algorithms: MSCANC lassical Test Algorithms: MSCAN Zero-One Algorithm[Breuer & Friedman 1976] Also known as MSCAN SAF is detected if the address decoder is correct (not all AFs are covered): Theorem: A test detects all AFs if it contains the march elements (ra,..,wb) and (rb,..,wa), and the Memory is initialized to the proper value before each march element Solid background (pattern) Complexity is 4N)}1();1();0();0({rwrwccccEE14119 VLSI Test Principles and ArchitecturesCh.

8 8 - Memory Testing & BIST - P. 19 Classical Test Algorithms: CheckerboardClassical Test Algorithms: Checkerboard Checkerboard Algorithm Zero-one algorithm with checkerboard pattern Complexity is 4N Must create true physical checkerboard, not logical checkerboard For SAF, DRF, shorts between cells, and half ofthe TFs Not good for AFs, and some CFs cannot be detected1 0 10 1 01 0 1EE14120 VLSI Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 20 Classical Test Algorithms: GALPATC lassical Test Algorithms: GALPAT Galloping Pattern (GALPAT) Complexity is 4N**2 only for characterization A strong test for most faults: all AFs, TFs, CFs, and SAFs are detected and located1. Write background 0;2. For BC = 0 to N-1{ Complement BC;For OC = 0 to N-1, OC != BC;{ Read BC; Read OC; }Complement BC; }3.

9 Write background 1;4. Repeat Step 2;BCEE14121 VLSI Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 21 Classical Test Algorithms: WALPATC lassical Test Algorithms: WALPAT Walking Pattern (WALPAT) Similar to GALPAT, except that BC is read only after all others are read. Complexity is 2N** Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 22 Classical Test Algorithms: SlidingClassical Test Algorithms: Sliding Sliding (Galloping) Row/Column/Diagonal Based on GALPAT, but instead of shifting a 1 through the Memory , a complete diagonal of 1s is shifted: The whole Memory is read after each shift Detects all faults as GALPAT, except for some CFs Complexity is 4N** Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 23 Classical Test Algorithms: ButterflyClassical Test Algorithms: Butterfly Butterfly Algorithm Complexity is 5 NlogN All SAFs and some AFs are detected1.

10 Write background 0;2. For BC = 0 to N-1{ Complement BC; dist = 1;While dist <= mdist/* mdist < col/row length */{ Read cell @ dist north from BC;Read cell @ dist east from BC;Read cell @ dist south from BC;Read cell @ dist west from BC;Read BC; dist *= 2; }Complement BC; }3. Write background 1; repeat Step 2;61945 ,1 02738EE14124 VLSI Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 24 Classical Test Algorithms: MOVIC lassical Test Algorithms: MOVI Moving Inversion (MOVI) Algorithm For functional and AC parametric test Functional (13N): for AF, SAF, TF, and most CF Parametric (12 NlogN): for Read access time 2 successive Reads @ 2 different addresses with different data for all 2-address sequences differing in 1 bit Repeat T2~T5 for each address bit GALPAT---all 2-address sequences)}0,0,1();1,1,0();0,0,1();1,1,0 ();0({rwrrwrrwrrwrw EE14125 VLSI Test Principles and ArchitecturesCh.