Modeling Latches and Flip-flops - Xilinx
Create and add the VHDL module with the SR_latch_dataflow code. 1-1-3. Develop a testbench (see waveform above) to test and validate the design. 1-1-4. Add the appropriate board related master XDC file to the project and edit it to include the related pins, assigning S input to SW0, R input to SW1, Q to LED0, and Qbar to LED1. 1-1-5.
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