MX25V1635F - MXIC

1 MX25V1635F . MX25V1635F . , 16M-BIT [x 1/x 2/x 4]. CMOS MXSMIO (SERIAL MULTI I/O). FLASH MEMORY. Key Features for Read, Erase and Program Operations Unique ID and Secure OTP Support Multi I/O Support - Single I/O, Dual I/O and Quad I/O. Program Suspend/Resume & Erase Suspend/Resume P/N: PM2257 Rev. , September 13, 2016. 1. MX25V1635F . Contents 1. 5. 2. GENERAL 6. Table 1. Additional 3. PIN CONFIGURATIONS .. 8. 4. PIN 8. 5. BLOCK 9. 6. DATA 10. Table 2. Protected Area 11. Table 3. 8K-bit Secured OTP 7. MEMORY 13. Table 4. Memory 8. DEVICE 14. 9. HOLD 16. 10. COMMAND 17. Table 5. Command 10-1. Write Enable (WREN).. 20. 10-2. Write Disable (WRDI).

2 21. 10-3. Read Identification (RDID).. 22. 10-4. Read Electronic Signature (RES).. 23. 10-5. Read Electronic Manufacturer ID & Device ID (REMS).. 24. 10-6. ID 25. Table 6. ID Definitions ..25. 10-7. Read Status Register (RDSR).. 26. Table 7. Status Table 8. Configuration Table 9. Dummy Cycle 10-8. Read Configuration Register (RDCR).. 31. 10-9. Write Status Register (WRSR).. 32. Table 10. Protection 10-10. Read Data Bytes (READ).. 36. 10-11. Read Data Bytes at Higher Speed (FAST_READ).. 37. 10-12. Dual Read Mode (DREAD).. 38. 10-13. 2 x I/O Read Mode (2 READ).. 39. 10-14. Quad Read Mode (QREAD).. 40. 10-15. 4 x I/O Read Mode (4 READ).. 41.

3 10-16. Burst 43. 10-17. Performance Enhance 44. 10-18. Sector Erase (SE).. 46. 10-19. Block Erase (BE32K).. 47. 10-20. Block Erase (BE).. 48. 10-21. Chip Erase (CE).. 49. 10-22. Page Program (PP).. 50. P/N: PM2257 Rev. , September 13, 2016. 2. MX25V1635F . x I/O Page Program (4PP).. 51. Power-down (DP).. 52. Secured OTP (ENSO).. 53. Secured OTP (EXSO).. 53. Security Register (RDSCUR).. 53. Table 11. Security Register 10-28. Write Security Register (WRSCUR).. 54. 10-29. Program Suspend and Erase 55. Table 12. Readable Area of Memory While a Program or Erase Operation is Table 13. Acceptable Commands During Program/Erase Suspend after Table 14.

4 Acceptable Commands During Suspend (tPSL/tESL not required)..56. 10-30. Program Resume and Erase 57. 10-31. No Operation (NOP).. 58. 10-32. Software Reset (Reset-Enable (RSTEN) and Reset (RST)).. 58. 10-33. High Voltage 60. 10-34. Read SFDP Mode (RDSFDP).. 61. 11. POWER-ON 62. 12. ELECTRICAL 63. Table 15. Absolute Maximum Table 16. Table 17. DC Table 18. AC Characteristics ..66. 13. OPERATING 68. Table 19. Power-Up/Down Voltage and 13-1. Initial Delivery 70. 14. ERASE AND PROGRAMMING 71. 15. LATCH-UP 71. 16. ORDERING 72. 17. PART NAME 73. 18. PACKAGE 74. 18-1. 8-pin SOP (150mil).. 74. 18-2. 8-pin SOP (200mil).. 75. 18-3. 8-land WSON (6x5mm).

5 76. 18-4. 8-land USON (4x3mm).. 77. 18-5. 8-land USON (2x3mm).. 78. 18-6. 24 ball TFBGA (6x8mm).. 79. 19. REVISION HISTORY .. 80. P/N: PM2257 Rev. , September 13, 2016. 3. MX25V1635F . Figures Figure 1. Serial Modes 14. Figure 2. Serial Input 15. Figure 3. Output 15. Figure 4. Hold 15. Figure 5. Hold Condition Operation .. 16. Figure 6. Write Enable (WREN) 20. Figure 7. Write Disable (WRDI) 21. Figure 8. Read Identification (RDID) 22. Figure 9. Read Electronic Signature (RES) 23. Figure 10. Read Electronic Manufacturer & Device ID (REMS) 24. Figure 11. Read Status Register (RDSR) 26. Figure 12. Program/Erase flow with read array 27. Figure 13.

6 Program/Erase flow without read array data (read P_FAIL/E_FAIL flag).. 28. Figure 14. Read Configuration Register (RDCR) 31. Figure 15. Write Status Register (WRSR) 32. Figure 16. WRSR 34. Figure 17. WP# Setup Timing and Hold Timing during WRSR when SRWD= 35. Figure 18. Read Data Bytes (READ) 36. Figure 19. Read at Higher Speed (FAST_READ) 37. Figure 20. Dual Read Mode Sequence (Command 3B).. 38. Figure 21. 2 x I/O Read Mode Sequence (Command BB).. 39. Figure 22. Quad Read Mode Sequence (Command 6B).. 40. Figure 23. 4 x I/O Read Mode 42. Figure 24. Burst 43. Figure 25. 4 x I/O Read enhance performance Mode 45. Figure 26. Sector Erase (SE) 46.

7 Figure 27. Block Erase 32KB (BE32K) Sequence (Command 52).. 47. Figure 28. Block Erase (BE) 48. Figure 29. Chip Erase (CE) 49. Figure 30. Page Program (PP) 50. Figure 31. 4 x I/O Page Program (4PP) 51. Figure 32. Deep Power-down (DP) Sequence and Release from Deep Power-down 52. Figure 33. Resume to Suspend 56. Figure 34. Suspend to Read/Program 57. Figure 35. Resume to Read 57. Figure 36. Software Reset 59. Figure 37. Reset 59. Figure 38. High Voltage Operation 60. Figure 39. Read Serial Flash Discoverable Parameter (RDSFDP) 61. Figure 40. Maximum Negative Overshoot 63. Figure 41. Maximum Positive Overshoot 63. Figure 42. Input Test Waveforms and Measurement 64.

8 Figure 43. Output 64. Figure 44. AC Timing at Device 68. Figure 45. Power-Down 69. Figure 46. Power-up 69. Figure 47. Power Up/Down and Voltage 70. P/N: PM2257 Rev. , September 13, 2016. 4. MX25V1635F . 16M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O). FLASH MEMORY. 1. FEATURES. GENERAL Auto Erase and Auto Program Algorithm Supports Serial Peripheral Interface -- Mode 0 and - Automatically erases and verifies data at selected Mode 3 sector or block 16,777,216 x 1 bit structure - Automatically programs and verifies data at se- or 8,388,608 x 2 bits (two I/O mode) structure lected page by an internal algorithm that automati- or 4,194,304 x 4 bits (four I/O mode) structure cally times the program pulse widths (Any page to Equal Sectors with 4K byte each, Equal Blocks with be programed should have page in the erased state 32K byte each, or Equal Blocks with 64K byte each first).

9 - Any Block can be erased individually Status Register Feature Single Power Supply Operation Command Reset - Operation Voltage: for Read, Erase and Program/Erase Suspend and Program/Erase Re- Program Operations sume Latch-up protected to 100mA from -1V to Vcc +1V Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device PERFORMANCE ID. High Performance - RES command for 1-byte Device ID. - Fast read - REMS command for 1-byte manufacturer ID and - 1 I/O: 80 MHz with 8 dummy cycles 1-byte device ID. - 2 I/O: 80 MHz with 4 dummy cycles, Support Serial Flash Discoverable Parameters equivalent to 160 MHz (SFDP) mode - 4 I/O: 80 MHz with 2+4 dummy cycles, Support Unique ID (Please contact local Macronix equivalent to 320 MHz sales for detail information).

10 - Fast program and erase time - 8/16/32/64 byte Wrap-Around Burst Read Mode HARDWARE FEATURES. Low Power Consumption SCLK Input Minimum 100,000 erase/program cycles - Serial clock input 20 years data retention SI/SIO0. - Serial Data Input or Serial Data Input/Output for 2. SOFTWARE FEATURES x I/O read mode and 4 x I/O read mode Input Data Format SO/SIO1. - 1-byte Command code - Serial Data Output or Serial Data Input/Output for Advanced Security Features 2 x I/O read mode and 4 x I/O read mode - Block lock protection WP#/SIO2. The BP0-BP3 status bit defines the size of the area - Hardware write protection or serial data Input/Out- to be software protection against program and put for 4 x I/O read mode erase instructions HOLD#/SIO3.