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PCI Express Base Specification Revision 1

PCI Express Base Specification Revision April 29, 2002. Revision Revision HISTORY DATE. Initial release. 4/29/02. PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein. Contact the PCI-SIG office to obtain the latest Revision of the Specification . Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be forwarded to: Membership Services E-mail: Phone: 1-800-433-5177 (Domestic Only).

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Transcription of PCI Express Base Specification Revision 1

1 PCI Express Base Specification Revision April 29, 2002. Revision Revision HISTORY DATE. Initial release. 4/29/02. PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein. Contact the PCI-SIG office to obtain the latest Revision of the Specification . Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be forwarded to: Membership Services E-mail: Phone: 1-800-433-5177 (Domestic Only).

2 503-291-2569. Fax: 503-297-1090. Technical Support DISCLAIMER. This draft Specification is being provided to you for review purposes pursuant to Article of the Bylaws of PCI-SIG. This draft Specification is subject to amendment until it is officially adopted by the Board of Directors of PCI-SIG. The Board of Directors may, at its discretion, initiate additional review periods, in which case you will be notified of the same. Pursuant to Article 14 of the Bylaws, this draft Specification is to be considered PCI-SIG Confidential until adopted by the Board of Directors.

3 All product names are trademarks, registered trademarks, or servicemarks of their respective owners. Copyright 2002 PCI-SIG. PCI Express BASE Specification , REV Contents PREFACE .. 17. OBJECTIVE OF THE Specification .. 18. DOCUMENT ORGANIZATION .. 18. DOCUMENTATION CONVENTIONS .. 19. TERMS AND ABBREVIATIONS .. 20. REFERENCE DOCUMENTS .. 25. 1. 27. A THIRD GENERATION I/O INTERCONNECT .. 27. PCI Express LINK .. 29. PCI Express FABRIC TOPOLOGY .. 30. Root Complex .. 31. 32. Switch .. 33. PCI Express -PCI Bridge .. 34. PCI Express FABRIC TOPOLOGY CONFIGURATION .. 34. PCI Express LAYERING OVERVIEW.

4 35. Transaction Layer .. 36. Data Link Layer .. 36. Physical 37. Layer Functions and Services .. 37. ADVANCED PEER-TO-PEER COMMUNICATION OVERVIEW .. 41. 2. TRANSACTION LAYER Specification .. 43. TRANSACTION LAYER OVERVIEW .. 43. ADDRESS SPACES, TRANSACTION TYPES, AND USAGE .. 44. Memory 44. I/O 45. Configuration Transactions .. 45. Message Transactions .. 45. PACKET FORMAT OVERVIEW .. 47. TRANSACTION DESCRIPTOR .. 48. 48. Transaction Descriptor Transaction ID Field .. 48. Transaction Descriptor Attributes Field .. 50. Transaction Descriptor Traffic Class Field .. 51.

5 TRANSACTION ORDERING .. 52. VIRTUAL CHANNEL (VC) MECHANISM .. 56. Virtual Channel Identification (VC ID) .. 58. VC Support Options .. 58. TC to VC Mapping .. 59. 3. PCI Express BASE Specification , REV VC and TC Rules .. 60. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION AND HANDLING .. 61. Transaction Layer Packet Definition Rules .. 61. TLP Digest 65. TLPs with Data Payloads - Rules .. 66. 67. 76. Handling of Received 78. 88. Baseline 88. Advanced Switching Support Message Group .. 98. ORDERING AND RECEIVE BUFFER FLOW CONTROL .. 99. Overview and 99. Flow Control Rules.

6 100. DATA INTEGRITY .. 109. 109. ECRC 109. ERROR FORWARDING .. 113. Error Forwarding Usage Model .. 113. Rules For Use of Data Poisoning .. 114. COMPLETION TIMEOUT MECHANISM .. 114. TRANSACTION LAYER BEHAVIOR IN DL_DOWN STATUS .. 115. TRANSACTION LAYER BEHAVIOR IN DL_UP STATUS .. 116. 3. DATA LINK LAYER Specification .. 117. DATA LINK LAYER OVERVIEW .. 117. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE .. 119. Data Link Control and Management State Machine 120. FLOW CONTROL INITIALIZATION 121. Flow Control Initialization State Machine 123. DATA LINK LAYER PACKETS (DLLPS).

7 125. Data Link Layer Packet 125. DATA INTEGRITY .. 130. 130. LCRC, Sequence Number, and Retry Management (TLP Transmitter).. 130. LCRC and Sequence Number (TLP Receiver) .. 142. 4. PHYSICAL LAYER Specification .. 149. INTRODUCTION .. 149. LOGICAL 149. Symbol 150. Framing and Application of Symbols to Lanes .. 153. Data Scrambling .. 156. Link Initialization and Training .. 157. Link Training and Status State Machine (LTSSM) .. 180. Link Training and Status State 183. Clock Tolerance Compensation .. 195. 4. PCI Express BASE Specification , REV Compliance 197. ELECTRICAL SUB-BLOCK.

8 198. Electrical Sub-Block 198. Electrical Signal Specifications .. 201. Differential Transmitter (Tx) Output Specifications .. 206. Differential Receiver (Rx) Input Specifications .. 211. 5. SOFTWARE INITIALIZATION AND CONFIGURATION .. 215. CONFIGURATION TOPOLOGY .. 215. PCI Express CONFIGURATION 216. PCI Compatible Configuration 217. PCI Express Enhanced Configuration 218. Root Complex Register 218. CONFIGURATION TRANSACTION RULES .. 219. Device 219. Configuration Transaction 219. Configuration Request Routing Rules .. 220. Generating PCI Special Cycles using PCI Configuration Mechanism #1.

9 221. CONFIGURATION REGISTER TYPES .. 221. PCI-COMPATIBLE CONFIGURATION REGISTERS .. 222. Type 0/1 Common Configuration Space .. 223. Type 0 Configuration Space 228. Type 1 Configuration Space 229. PCI POWER MANAGEMENT CAPABILITY STRUCTURE .. 232. MSI CAPABILITY 234. PCI Express CAPABILITY STRUCTURE .. 234. PCI Express Capability List Register (Offset 00h) .. 235. PCI Express Capabilities Register (Offset 02h).. 235. Device Capabilities Register (Offset 04h).. 237. Device Control Register (Offset 08h).. 241. Device Status Register (Offset 0Ah) .. 244. Link Capabilities Register (Offset 0Ch).

10 246. Link Control Register (Offset 10h).. 248. Link Status Register (Offset 12h) .. 250. Slot Capabilities Register (Offset 14h).. 251. Slot Control Register (Offset 18h).. 253. Slot Status Register (Offset 1Ah).. 255. Root Control Register (Offset 1Ch).. 256. Root Status Register (Offset 20h) .. 257. PCI Express EXTENDED CAPABILITIES .. 258. Extended Capabilities in Configuration Space .. 259. Extended Capabilities in the Root Complex Register Block .. 259. PCI Express Enhanced Capability 259. ADVANCED ERROR REPORTING CAPABILITY .. 260. Advanced Error Reporting Enhanced Capability Header (Offset 00h).


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