Platform Runtime Mechanism - Unified Extensible Firmware ...

1 Platform Runtime Mechanism Version: Date: November 2020 Disclaimers The material Contained herein is not a license, either expressly or impliedly, to any intellectual property owned or Controlled By any of the authors or developers of this material or to any Contribution thereto. The material Contained herein is provided on an "AS IS"Basis and, to the maximum extent permitted By applicable law, this information is provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material hereby disclaim all other warranties and Conditions, either express, implied or statutory, including, But not limited to, any (if any) implied warranties, duties or Conditions of merchantability, of fitness for a particular purpose, of accuracy or Completeness of responses, of results, of workmanlike effort, of lack of viruses and of lack of negligence, all with regard to this material and any Contribution thereto.

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3 Copyright 2020, Unified Extensible Firmware Interface (UEFI) Forum, Inc. All Rights Reserved. The UEFI Forum is the owner of all rights and title in and to this work, including all copyright rights that may exist, and all rights to use and reproduce this work. Further to such rights, permission is hereby granted to any person implementing this specification to maintain an electronic version of this work accessible by its internal personnel, and to print a copy of this specification in hard copy form, in whole or in part, in each case solely for use by that person in connection with the implementation of this Specification, provided no modification is made to the Specification. 3 Table of Contents TABLE OF CONTENTS .. 3 REFERENCES .. 7 1. INTRODUCTION .. 8 BACKGROUND ON SYSTEM MANGEMENT MODE (SMM) .. 8 ISSUES WITH SMM PROBLEM STATEMENT.

4 8 SMI and Perf/QoS degradation .. 8 SMI and Firmware complexity .. 9 ACPI and SMM .. 9 SUMMARY .. 9 2. SMM USAGES .. 10 CATEGORIES OF SMIS .. 12 CATEGORY 1 USAGES .. 13 CATEGORY 3 USAGES .. 14 3. Platform Runtime Mechanism OVERVIEW .. 15 PRM REQUIREMENTS .. 16 PRM AND UEFI .. 17 PRM LOADING AND INVOCATION .. 17 PRMT TABLE OVERVIEW .. 17 4. ACPI TABLES .. 19 Platform Runtime Mechanism TABLE (PRMT) .. 19 PRM Module Information Structure .. 19 PRM Handler Information Structure .. 20 EXPLANATION OF BUFFERS USED .. 21 Static Data Buffer .. 21 ACPI Parameter Buffer .. 21 Module Runtime MMIO Ranges .. 22 5. INVOCATION OF PRM HANDLERS .. 24 DIRECT CALL VS ASL BASED INVOCATION .. 24 INVOCATION Mechanism - OVERVIEW .. 24 DIRECT INVOCATION .. 25 ASL (_DSM) BASED INVOCATION .. 25 CONTEXT BUFFER.

5 25 6. PRM SOFTWARE ORGANIZATION .. 27 PRM MODULE IMAGE FORMAT .. 27 Export Descriptor Structures .. 28 PRM MODULE LOADER .. 29 Firmware PRM Loader .. 29 OS PRM Loader .. 29 PRM HANDLER .. 30 Overview .. 30 Function Signature .. 30 7. SERVICABLE PRM .. 32 HIGH-LEVEL FLOWS .. 32 Update Lock/Unlock .. 32 INSTALLATION IN WINDOWS .. 34 Persisting PRM Module Updates Across Reboot/KSR .. 34 ROLLBACK .. 34 8. APPENDIX A: PRM HANDLER _DSM INVOCATION .. 35 PRM OPREGION DEFINITION .. 35 Declaring Fields in the PRM Operation Region .. 36 Declaring and Using a PRM Data Buffer .. 36 PRM INVOCATION EXAMPLE .. 38 Example ASL Code for Locking Updates .. 40 Example ASL Code for Unlocking Updates .. 40 9. APPENDIX B: _OSC AND OPREGION .. 42 Platform -WIDE OSPM CAPABILITIES .. 42 PRM OPERATION REGION .. 42 5 TERMINOLOGY Term Definition ACPI Advanced Configuration and Power Interface AP Application Processor.

6 All the processor threads other than Startup-BSP APIC Advanced Programmable Interrupt Controller residing in the processor agents to generate and accept interrupt messages from other processor and I/O agents. Sometimes it is referred as Local APIC. ARS Address Range Scrubbing (ARS) allows Platform to communicate persistent memory errors to system software. See BMC IPMI compliant Board Management Controller. BWG BIOS Writer s Guide BSP Bootstrap Processor CSP Cloud Service Provider DDDC Double Device Data Correction DMI Proprietary data path between IIO and South bridge. DPC DIMMs Per Channel ESRT The EFI System Resource Table (ESRT) provides a Mechanism for identifying integrated device and system Firmware resources for the purposes of targeting Firmware updates to those resources. GPIO General Purpose Input/Output GUID Globally Unique Identifier HPC High Performance Computing IIO Integrated IO PCI Host Bridge logic that has been integrated in the CPU complex.

7 IPMI Intelligent Platform Management Interface KSR Kernel Soft Reboot KTI Keizer Technology Interface Legacy Processor The processor that is connected to PCH via DMI link and manages the boot devices LPC Bus Low Pin Count connection used to connect to the BMC, super I/O device, and TPM. MCA Machine Check Architecture Microcode CPU s Firmware coordinating CPU s actions, sometimes abbreviated as uCode MMIO Memory Mapped IO NFV Network Function Virtualization NMI Non-maskable Interrupts OS Operating System OOB Out of Band (such as via a BMC) OSPM Operating System Directed Power Management PCH Platform Controller Hub. Some might call this a Peripheral Controller Hub Pcode Code executing on PCU PCU Power Control Unit, a controller inside the processor that performs power and other power management functions Term Definition PMEM Persistent Memory (Such as Intel 3D XPoint / Non-Volatile DIMMs) Powergood Reset A reset during which power is removed.

8 Using a power-button. RTC power and Standby power is not affected. QoS Quality of Service RAS Reliability-Availability-Serviceabilty SCI System Control Interrupt as defined in ACPI Specification SDDC Single Device Data Correction SMBIOS System Management BIOS SMI System Management Interrupt SMM System Management Mode SW Software UEFI Unified Extensible Firmware Interface 7 References ACPI Specification UEFI Specification 1. Introduction Background on System Mangement Mode (SMM) System Management Mode (SMM) is an operating mode in the x86 computer architecture. SMM code is written within the context of the system Firmware and typically used for system-wide functions which are highly Platform and silicon specific. Some examples would be RAS ( Hardware Errors such as memory ECC, or to take corrective hardware actions to extend system uptime), power management, execution of OEM proprietary code, Platform hardware events and implementation of hardware workarounds.

9 In order to enter SMM, a System Management Interrupt (SMI) must be generated by a Platform events. SMI is a high priority, non-maskable, broadcast interrupt. On receipt of this interrupt, the processors in the system save their context in SMRAM and transition to SMM to execute the corresponding SMI Handler for the given event. The SMI handler code then sets up its own environment (page tables, IDTs etc.), identifies the source of SMI and handles that event accordingly. The SMI handler is placed by the Platform BIOS during BOOT to a special area of memory called System Management RAM (SMRAM). SMRAM is invisible to OS/VMM. A processor executing in the 0-3 ring privilege levels will not be able to read from or write to SMRAM space. When the processor switches to SMM on receipt of an SMI, then processor executes code out of the SMRAM area.

10 There are two different categories of SMI sources, asynchronous and synchronous. SMIs due to Platform and hardware events are asynchronous in nature. Software SMIs are invoked by writing to Port 0xB2 (in Intel Architecture platforms) and are synchronous in nature. The document describes the Platform Runtime Mechanism (PRM) as a means to remove usage of certain classes of SMI handlers. PRM, along with Native OS drivers and offload to other hardware engines such as a Baseboard Management Controller (BMC) offer a path to eliminate Runtime SMIs. Issues with SMM Problem Statement As described in the previous section, SMM mode of operation has the following key attributes: 1. SMRAM (a memory space where SMI Handlers reside) is a Black Box to OS/VMM. 2. SMI Handlers run with their own page tables and accessibility to all system resources (higher privileged than ring-0).