Transcription of 完全デジタルPLL技術の動向 - el.gunma-u.ac.jp
1 11 PLL ( ) ( )MWE2009 RF 0 Review of All Digital PLL (ADPLL)2 23 34AD PLL (AllDigitalPhaseLocked Loop: ADPLL PLL CMOSSOC BogdanStaszewski TexasInstruments ADPLL CMOSSOC RF 5 56 (Fref) FCW (Frequency Command Word) 77 PLL - - - 8 PLL (ADPLL))
2 = 9 910 SOC CMOS 11 TDC DCO DCO 12 - - 13 ADPLL Bogdan Staszewski CMOS VTime VTime VTim 14 CMOS CMOS LSI ADPLL CMOS Vout = = = 0 Vin = ) when Vin = 1 ( )b) when Vin = 0 Vout = = Vout= 15 -ADPLL - DCO -TDC 16 -ADPLL - DCO -TDC 1617 FoutFout = FCW x FREF(FCW)18 -- Time-to-Digital Converter Digital Controlled Oscillator 19 -ADPLL - DCO -TDC 1920 (DCO) VCO (Voltage Controlled Oscillator) Digitally-Controlled Oscillator.
3 DCO 21 MOS n Vc1 VcnVcVgs= Vgs= 22 MOS / /T / ion 23 w/ w/o 24 NTW25 ADPLL 3 PVTA cquisitionTracking 26 Tracking Acquisition Tracking Acquisition Tracking 1 2 FrequencyTimeFrequencyTime 27 01 NTW NTW NTW NTW.
4 Normalized Tuning Word Oscillation Tuning Word (OTW)28 )(NTW122 +=1121 =NTW 01 NTW NTWNTW1 NTW2 E NTW E 111 NTW = 29 TrackingControl log2( 2exp 1exp) 10 + log2( 1exp)bit shift 1 2 2 x bit shift bit shiftNTW1211 +=)(1211 +=1112 NTW = NTW1 NTW2 NTW NTW Control 30 2 3131 / 32 -ADPLL - DCO -TDC 3233 = / = - - = = / = / 34 Time-to-Digital Converter.
5 TDC) StartStopDoutTDC TStartStop CMOS TDC 1988 VLSI Circuit Symp 35 TDC StartStopD0=1D1=1D2=1D3=0D4=0 Timing chartThermometer code binary codeEncoder CMOS TStartStop36 - DCOFref - FrefDCO - INVVWtTF /2 INVVtT / DCO DCO 37 3738 ADPLL DCO TDC ADPLL 39 ADPLL FCWADPLL TDC DCO DCO NTDC_q(f)NDCO_q(f)NDCO_a(f)Type 2 PLL40 TDC FCW2RR22 RRq_TDCfsfsfsfH +++=-60-50-40-30-20-1001E+001E+021E+041E +061E+08 ADPLL TDC DCO DCO NTDC_q(f)NDCO_q(f)NDCO_a(f)41 DCO FCW2RR2q_DCOfsfss2H ++=-200-180-160-140-120-100-80-60-40-200 1E+001E+021E+041E+061E+08 ADPLL TDC DCO DCO NTDC_q(f)NDCO_q(f)NDCO_a(f)42 DCO FCW2RR22a_DCOfsfssH ++=-90-80-70-60-50-40-30-20-100101E+001E +021E+041E+061E+08 ADPLL TDC DCO DCO NTDC_q(f)NDCO_q(f)NDCO_a(f)43 FCWNTDC_q(f)NDCO_q(f)NDCO_a(f)
6 +00 +01 +02 +03 +04 +05 +06 +07 +08 +09[dB] [Hz]DCO_qDCO_aTDC_qADPLL TDC DCO DCO 44 4445 IC x x RxTx 46 Rx, Tx Rx, Tx ADPLL RxDigitalTx PLL 47 ADPLL ADPLL RF (Phase Trajectory Error)ADPLL E [1] R. B. Staszewski, et. Al., RF Built-in Self Test of a Wireless Transmitter, IEEE Trans. CAS II (Feb. 2007).48 4849 : , IntelCorp. BM Corp. MIT,UCSD Universityof California SanDiego UCLA Universityof California LosAngeles EpochMicroelectronics Pavia MediaTek Inc.
7 : 50 CMOS RF - - - - - Analog people are from Mars, RF people are from processing people are from ADPLL - - Bluetooth - 52 53 TDC PMOS Gated Ring Oscillator (GRO) MIT ( SiTime) Dr. M. Perrot 54 TDC 55 TDCref(t)div(t) (t)Count[k] 56 Wp:Wn=3:1Wp=9 mL=180nmWn=3 mL=180nmVdd= tsmc cmos 57AB res=2 ( ) = VddPMOSNMOSVddPMOSNMOSPMOSNMOSAB VddPMOSNMOSOFFONPMOSNMOSPMOSNMOSONVddPMO SNMOSLCLCOFFONVddPMOSNMOSLCVddPMOSNMOSLC OFFONVddPMOSNMOSLCOFFONLCLCOFFONVddVdd 000 VddVddPMOSNMOSLCOFFONLCLCOFFONVdd 58 Wp:Wn=3.
8 1 Vdd= Wp=9 mL=180nmWp=3 mL=180nm GRO ( )tsmc cmos 59 res ACD VddPMOSNMOSVddPMOSNMOS res=2 ( ) = CL GRO PMOS OFF0 VddPMOSNMOSLCON0 1/2 Vdd1/2 Vdd VddVddPMOSNMOSOFFONLCVddPMOSNMOSLCONONON ON 60 res ACD VddPMOSNMOSVddPMOSNMOS res=2 ( ) = CL GRO PMOS OFF0 VddPMOSNMOSLCON0 1/2 Vdd1/2 Vdd VddVddPMOSNMOSOFFONLCVddPMOSNMOSLCONONON ONHHLOFFON 61 res ACD VddPMOSNMOSVddPMOSNMOS res=2 ( ) = CL GRO PMOS OFF0 VddPMOSNMOSLCON0 1/2 Vdd1/2 Vdd VddVddPMOSNMOSOFFONLCVddPMOSNMOSLCONONON ONLHLONON 62 res ACD VddPMOSNMOSVddPMOSNMOS res=2 ( ) = CL GRO PMOS OFF0 VddPMOSNMOSLCON0 1/2 Vdd1/2 Vdd VddVddPMOSNMOSOFFONLCVddPMOSNMOSLCONONON ONLLHONOFF 63 res ACD VddPMOSNMOSVddPMOSNMOS res=2 ( ) = CL GRO PMOS OFF0 VddPMOSNMOSLCON0 1/2 Vdd1/2 Vdd VddVddPMOSNMOSOFFONLCVddPMOSNMOSLCONONON ONLHLONON 64 GRO ( )Wp:Wn=3:1 Vdd= Wp=9 mL=180nmWp=3 mL=180nm AEFtsmc cmos 65 , 66 ADPLL ( 2 BW= *fR*sqrt(1/2+1/2*sqrt(1+4* ^2/ ^4)) =)
