Example: marketing

QUAD 2 INPUT NAND GATES - CMOS 4000

1/7 September 2001nPROPAGATION DELAY TIMEtPD= 60ns (Typ.) at VDD= 10 VnBUFFERED INPUTS AND OUTPUTSnSTANDARDIZED SYMMETRICAL OUTPUTCHARACTERISTICSnQUIESCENT CURRENT SPECIFIED UP TO20Vn5V, 10V AND 15V PARAMETRIC RATINGSnINPUT LEAKAGE CURRENTII= 100nA (MAX) AT VDD= 18V TA=25 Cn100% TESTED FOR QUIESCENT CURRENTnMEETS ALL REQUIREMENTS OF JEDECJESD13B STANDARD SPECIFICATIONSFOR DESCRIPTION OF B SERIES CMOSDEVICES DESCRIPTIONThe HCF4011B is a monolithic integrated circuitfabricatedinMetalOxideSemiconduct ortechnology available in DIP and SOP HCF4011B quad 2 INPUT nand gate provides the systemdesigner with directimplementation of the nand function andsupplement the existing family of cmos GATES . Allinputs and outputs are 2 INPUT nand GATEPIN CONNECTIONORDER CODESPACKAGETUBET & RDIPHCF4011 BEYSOPHCF4011BM1 HCF4011M013 TRDIPSOPHCF4011B2/7 INPUT EQUIVALENT CIRCUITLOGIC DIAGRAMPIN DESCRIPTIONTRUTH TABLEABSOLUTE MAXIMUM RATINGSA bsolute Maximum Ratings are those values beyond which damage to the device may occur.

september 2001 1/7 propagation delay time tpd = 60ns (typ.) at vdd = 10v buffered inputs and outputs standardized symmetrical output characteristics quiescent current specified up to

Tags:

  Input, Gate, Cmos, Quad, Nand, Quad 2 input nand gates

Information

Domain:

Source:

Link to this page:

Please notify us if you found a problem with this document:

Other abuse

Advertisement

Transcription of QUAD 2 INPUT NAND GATES - CMOS 4000

1 1/7 September 2001nPROPAGATION DELAY TIMEtPD= 60ns (Typ.) at VDD= 10 VnBUFFERED INPUTS AND OUTPUTSnSTANDARDIZED SYMMETRICAL OUTPUTCHARACTERISTICSnQUIESCENT CURRENT SPECIFIED UP TO20Vn5V, 10V AND 15V PARAMETRIC RATINGSnINPUT LEAKAGE CURRENTII= 100nA (MAX) AT VDD= 18V TA=25 Cn100% TESTED FOR QUIESCENT CURRENTnMEETS ALL REQUIREMENTS OF JEDECJESD13B STANDARD SPECIFICATIONSFOR DESCRIPTION OF B SERIES CMOSDEVICES DESCRIPTIONThe HCF4011B is a monolithic integrated circuitfabricatedinMetalOxideSemiconduct ortechnology available in DIP and SOP HCF4011B quad 2 INPUT nand gate provides the systemdesigner with directimplementation of the nand function andsupplement the existing family of cmos GATES . Allinputs and outputs are 2 INPUT nand GATEPIN CONNECTIONORDER CODESPACKAGETUBET & RDIPHCF4011 BEYSOPHCF4011BM1 HCF4011M013 TRDIPSOPHCF4011B2/7 INPUT EQUIVALENT CIRCUITLOGIC DIAGRAMPIN DESCRIPTIONTRUTH TABLEABSOLUTE MAXIMUM RATINGSA bsolute Maximum Ratings are those values beyond which damage to the device may occur.

2 Functional operation under these conditions isnot voltage values are referred to VSSpin OPERATING CONDITIONSPIN NoSYMBOLNAME AND FUNCTION1, 2, 5, 6, 8,9, 12, 13A, B, C, D, E,F, G, HData Inputs3, 4, 10, 11J, K, L, MData Outputs7 VSSN egative Supply Voltage14 VDDP ositive Supply VoltageINPUTSOUTPUTSA, C, E, GB, D, F, HJ, K, L, MLLHLHHHLHHHLS ymbolParameterValueUnitVDDS upply to +22 VVIDC INPUT to VDD+ INPUT Current 10mAPDP ower Dissipation per Package200mWPower Dissipation per Output Transistor100mWTopOperating Temperature-55 to +125 CTstgStorage Temperature-65 to +150 CSymbolParameterValueUnitVDDS upply Voltage3to20 VVII nput Voltage0 to VDDVTopOperating Temperature-55 to 125 CHCF4011B3/7DC SPECIFICATIONSThe Noise Margin for both 1 and 0 level is: 1V min.

3 With VDD=5V, 2V min. with VDD=10V, min. with VDD=15 VDYNAMIC ELECTRICAL CHARACTERISTICS(Tamb=25 C, CL= 50pF, RL= 200K ,tr=tf= 20 ns)(*) Typical temperature coefficient for all VDDvalue is %/ ConditionValueUnitVI(V)VO(V)|IO|( A)VDD(V)TA=25 C-40 to 85 C -55 to 125 Current0 A0 Level OutputVoltage0/5< < < Level OutputVoltage5/0< < < Level < < <115111111 VILLow Level < < <115444 IOHO utput DriveCurrent0 < < < < SinkCurrent0 < < < LeakageCurrent0/18 Any Input18 10-5 1 1 ACII nput CapacitanceAny ConditionValue (*)UnitVDD(V) Delay Time5125250ns1060120154590tTLHtTHLO utput Transition Time5100200ns1050100154080 HCF4011B4/7 TEST CIRCUITCL= 50pF or equivalent (includes jig and probe capacitance)RL= 200K RT=ZOUTof pulse generator (typically 50 )WAVEFORM.

4 PROPAGATION DELAY TIMES(f=1 MHz; 50% duty cycle)HCF4011B5 DIP-14 MECHANICAL DATAP001 AHCF4011B6 (typ.) (max.)SO-14 MECHANICAL DATAPO13 GHCF4011 BInformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for theconsequences of use of such inform ation nor for any infringe ment of patents or other righ ts of third parties which may result fromits use. No license is granted by implication or otherwise unde r any patent or patent rig hts of STMicroelectronics. Specificationsmentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all in formationpreviously supplied. STMicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices orsystems with out express written approval of STMicroel ectronics.

5 The ST logo is a registered trademark of STMicro electronics 2001 STMicroelectronics - Printed in Italy - All Rights ReservedSTMicroelectroni cs GROUP OF COMPANIESA ustralia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - MoroccoSingapore - Spain - Sweden - Swit zerland - United Kingdom http://w


Related search queries