Quartus® Prime はじめてガイド - TimeQuest によるタイミ …

1 ALTIMA Company, MACNICA, Inc. ELSENA,Inc. quartus Prime TimeQuest 2018 3 quartus Prime TimeQuest / Rev. 2 2018 3 2/32 ALTIMA Company, MACNICA, Inc. / ELSENA,Inc..3 SDC ..5 Analysis & Synthesis .. 5 TimeQuest Timing Analyzer SDC .. 5 2-2-1.. 8 2-2-2. I/O .. 18 2-2-3.. 26 SDC .. 30 SDC .. 30 .. 30 .. 31 .. 32 quartus Prime - TimeQuest / Rev. 2 2018 3 3/32 ALTIMA Company, MACNICA, Inc.

2 / ELSENA,Inc. quartus quartus Prime / quartus II FPGA 5. FPGA/CPLD SDC ASIC Synopsys Design Constraints (SDC) FPGA/CPLD quartus Prime Fitter TimeQuest Timing Analyzer IP (Intellectual Property) IP IP SDC SDC SDC quartus Prime TimeQuest Timing Analyzer SDC quartus Prime Standard Edition quartus Prime - TimeQuest / Rev.

3 2 2018 3 4/32 ALTIMA Company, MACNICA, Inc. / ELSENA,Inc. PLL (On-Chip Memory) quartus Prime - TimeQuest / Rev. 2 2018 3 5/32 ALTIMA Company, MACNICA, Inc. / ELSENA,Inc. SDC SDC Analysis & Synthesis quartus Prime Processing Start Start Analysis & Synthesis Analysis & Synthesis Fitter Analysis & Synthesis TimeQuest Timing Analyzer SDC 1.

4 quartus Prime Tools TimeQuest Timing Analyzer TimeQuest Timing Analyzer 2. TimeQuest Create Timing Netlist quartus Prime Analysis & Synthesis Fitter Analysis & Synthesis Netlist Create Timing Netlist Input netlist Post-map OK Fitter Netlist Create Timing Netlist Input netlist Post-fit OK Task Create Timing Netlist quartus Prime quartus Prime quartus Prime - TimeQuest / Rev.

5 2 2018 3 6/32 ALTIMA Company, MACNICA, Inc. / ELSENA,Inc. 3. TimeQuest File New SDC File SDC SDC quartus Prime Windows Detach window quartus Prime TimeQuest SDC Detach window quartus Prime Netlist Create Timing Netlist Tasks Create Timing Netlist Analysis & Synthesis TimeQuest quartus Prime - TimeQuest / Rev.

6 2 2018 3 7/32 ALTIMA Company, MACNICA, Inc. / ELSENA,Inc. 4. I/O SDC File Save As .sdc TimeQuest SDC Edit Insert Constraint SDC Editor quartus Prime - TimeQuest / Rev. 2 2018 3 8/32 ALTIMA Company, MACNICA, Inc.

7 / ELSENA,Inc. 2-2-1. FPGA/CPLD Base Clock FPGA/CPLD Generated Clock PLL PLL # quartus Prime TimeQuest Base Clock create_clock FPGA/CPLD Base Clock SDC Edit Insert Constraint Create Clock Create Clock

8 Clock name TimeQuest SDC TimeQuest quartus Prime Period Name Finder # SDC SDC Editor quartus Prime - TimeQuest / Rev. 2 2018 3 9/32 ALTIMA Company, MACNICA, Inc. / ELSENA,Inc. Waveform edges 50 Rising Falling 50 Targets TimeQuast Name Finder Name Finder quartus Prime Node Finder Name Finder SDC Cell LUT I/O PLL Pin Cell Net Pin Port Port Pin Name Finder Collections Port Pin

9 Collections get_ports get_pins get_clocks all_clocks all_registers all_inputs all_outputs quartus Prime - TimeQuest / Rev. 2 2018 3 10/32 ALTIMA Company, MACNICA, Inc. / ELSENA,Inc. Insert SDC SDC Base Clock Collections * data* Case-insensitive Filter Hierarchical Filter Compatibility mode > SDC SDC Editor quartus Prime - TimeQuest / Rev.

10 2 2018 3 11/32 ALTIMA Company, MACNICA, Inc. / ELSENA,Inc. Generated Clock create_generated_clock PLL FPGA/CPLD Generated Clock SDC Edit Insert Constraint Create Generated Clock Create Generated Clock Insert SDC PLL PLL PLL Name Finder SDC quartus