RF Circuits – Design & Analysis

1 Dr. T. K. Bhattacharyya,Dept. of E&ECERF Circuits Design & AnalysisDr. T K BhattacharyyaDr. T K BhattacharyyaE & ECE T. K. Bhattacharyya,Dept. of E&ECEB asics of RFDr. T. K. Bhattacharyya,Dept. of E&ECEWhat is RF? Why Lumped parameters models failed .. Kirchoff's to Maxwell Failure of two port circuit parameter (Z, Y,ABCD) .. Scattering parameter( S-parameter) on the basis of Maxwell equation comes in ..Dr. T. K. Bhattacharyya,Dept. of E&ECEA pplication area of the RF-IC designer Wireless communication Radar Navigation Remote sensing RF identification Automobile and Highways Sensors: Medical Radio- astronomy and space explorationDr.

2 T. K. Bhattacharyya,Dept. of E&ECEB eauty of RF- IC Design : Link between Microwave Engineer and Design Engineerkirchoff s lawTotal voltage around a loop is zero( KVL)No net current build up at any node(KCL) If & =0, (c ) infinitely fast wave propagation of wave gives KVL and KCL As the physical dimension of circuit element & sub- circuit in a IC chip is very less (even less than 1/10thof [ 30 cm in air at 1 GHz] ) , so finiteness of the speed of lightis not noticeableinside chip, so a full transmission line ( Microwave) for on-chip designand Analysis is generally s law is well suited for on-chip Design But for interfacing the RF signals in / out of the chip, we need connectors, boards, cables etc.

3 Where transmission-line effects cannot be ignoredDr. T. K. Bhattacharyya,Dept. of E&ECEC omparison of Analog and RF/MW( Analog [Low frequency<100 MHz] )( RF/MW[ High frequency>100 MHz] )ConductorCapacitorResistorInductorSimpl e wire Microstrip lineCeramicCarbonThin Film SMD Film SMD WoundThin Film SMD On Discrete PCB componentDr. T. K. Bhattacharyya,Dept. of E&ECEC omparison of Analog and RF/MW( Analog [Low frequency<100 MHz] )( RF/MW [High frequency>100 MHz] )1. On Performance BasedA. Small signal AC equivalent circuit Analysis B. Linearity C. StabilityD. Noise (on few cases)A. Small signal AC equivalent circuit Analysis with parasitic Good circuit ModelingB.

4 MatchingE. Linearity D. StabilityC. Noise F. Sensitivity G. Dynamic range Dr. T. K. Bhattacharyya,Dept. of E&ECERF circuit & Systems Design Issues Phase shift of the signal is significant over the extent of the component because it s size is comparable with the wavelength. The reactance of the circuit must be accounted for, particularly those associated with the parasitic of the active devices. circuit losses causes degradation of Q, reduction of frequency selectivity and noise performance. Noise especially arising from the circuit can be significant and it s effect needs to be modeled. Electromagnetic radiation capacitive coupling and substrate coupling significantly alter the performance of the circuit .

5 Reflection issues, because circuit size is of the order of a wavelength. circuit Design should take care to ensure reflections do not cause any loss of gain, power, or failure of components. Nonlinearity which causes distortion and unwanted frequency components is undesirable, but it may become essential part of the circuit operation, as in mixing or local T. K. Bhattacharyya,Dept. of E&ECEHigh Frequency Device modelingSilicon TechnologiesBiCMOSMOSB ipolarJunction Isolated BJTsDielectricIsolatedPMOSNMOSCMOSDr. T. K. Bhattacharyya,Dept. of E&ECEHigh Frequency Device modeling (contd.)Visualization of Process FlowProtective OvercoatCVD Oxidep-epip-substraten+n+Gate oxidepolyFOXcontactMetal-1viaMetal-2Dr.

6 T. K. Bhattacharyya,Dept. of E&ECES tandard Digital CMOS is hardly the ideal medium for RF ICs, because of : Lossy Silicon substrate Large source/drain parasitics High device noise and poor 1/f noise performance Series gate resistanceBut, Device scaling ..faster CMOS fT(and fmax) ..range of 60 GHz doubles roughly every 3 years. CMOS is cost effective Both digital & analog block can be designed on same substrate High linearity; Low distortion Low power consumption On-chip realization of passive inductors and capacitorsCMOSBJT Symmetric behavior. Better linearity (Higher signal swing). Higher fTat sub-micron feature size.

7 Better scaling properties. Low power (no gate DC current). Higher gmfor same bias. High fT. Low thermal and 1/fnoise, but input current noise. Lower DC offset . No body effect. Lower overdrive (Low VCE sat).WHY CMOS FOR RF-IC?Dr. T. K. Bhattacharyya,Dept. of E&ECERRR polyCgsCgdCdsCsub To calculate magnetic coupling between two adjacent metal line, interlayer capacitance , EMI between subcircuits & on-chip passive component (such as inductor and MIM capacitor) , the Maxwell EM equation is required ( Challenging issue !!!)Dr. T. K. Bhattacharyya,Dept. of E&ECERF CMOS MODELLINGM aximum unit power gain Maximum unit power gain frequencyfrequencyMaximum CutMaximum Cut--off frequencyoff frequency Standard (digital oriented) MOS models do not allow for RFStandard (digital oriented) MOS models do not allow for RFIn RF, Cgs ( whose effect negligible in low frequency analog) affects the matching with successive blocks.

8 Frequency dependence of Transconductance(gm)Dr. T. K. Bhattacharyya,Dept. of E& Lee P-68,70gcoxCC=cbsiCC=sbojsb1/ 2sb0 CCV(1)=+ dbojd B1/2db0 CCV(1)=+ Long channel effectnoxgst21Id2WC(VV)L= gst3nfT222L(VV ) = Short channel effectndcV1 = + dvdy =dIdIQWV(y)=,dInc1dvdvI(1. ) WQ(y)dydy+= noxdgstgstc2 CWI(VV)VVL2(1)L = + noxgstgst2CW(VV )2[1(VV )] L = + gstcmoxsclgstc2(VV )11 LgWCV2(VV )1L + = + scln cV= , fTindependent of overdrive voltagegst(VV ) fTinversely proportional to LRF CMOS MODELLINGRF CMOS MODELLINGDr. T. K. Bhattacharyya,Dept. of E&ECEN oise Thermal Noise-Brownian motion of thermally agitated charge carriers-generated in every physical resistor- pure reactive components generate no thermal noiseThermal Noise in MOSFETTh most significant source of noise Channel Noise:In2 = 4kT gm ~1 at a zero VDS for long channel device, 2/3 at saturation, 2-3 for short channel transistorSignificance :The significance of noise performanceof a circuit is the limitation it places on thesmallest input signals(MDS) the circuit can handle before the noise degrades the quality of output T.

9 K. Bhattacharyya,Dept. of E&ECE this noise is negligible at low frequency, but can dominate at RF ~ 4/3 in long device- both drain and gate noise share a common origin and they are correlatedShot Noise-Gaussian white process associated with the transfer of charge across an energy barrier - due to DC current through p-n junction, gate channelFlicker noise in MOSFET-random trapping of charge at oxide interface- modeled as a voltage source in series with gateGate induced noiseThermal agitation of channel charge cause fluctuation of channel potential. This couples capacitively with gate terminal, leading to gate noise Dr.

10 T. K. Bhattacharyya,Dept. of E&ECEN oise figureNoise figure( )Noise figure of cascaded two stage case it can be shownFor m- stages NF of each stages is calculated with respect to the output impedance of previous stages The noise is contributed by each stage decreases as the gain preceding the stages increase That s why the first stage of any system should have higher gain with low noise figure ( PRIME CRITERION FOR LOW NOISE AMPLIFIER (LNA) Design OF A RECEIVER)Dr. T. K. Bhattacharyya,Dept. of E&ECES ensitivityDr. T. K. Bhattacharyya,Dept. of E&ECED ynamic RangeDr. T. K. Bhattacharyya,Dept. of E&ECEM odeling of Arbitrary ShapedRF Spiral Inductors for circuit Simulation Complex field coupling between turns.