RISC-V External Debug Support Version 0.13.2 ...

1 RISC-V External Debug SupportVersion :Tim SiFive, SiFive, Mar 22 09:06:04 2019 -0700 Contributors to all versions of the spec in alphabetical order (please contact editors to suggest cor-rections): Bruce Ableidinger, Krste Asanovi c, Allen Baum, Mark Beal, Alex Bradbury, ChuanhuaChang, Zhong-Ho Chen, Monte Dalrymple, Vyacheslav Dyachenko, Peter Egold, Markus Goehrle,Robert Golla, John Hauser, Richard Herveille, Yung-ching Hsiao, Po-wei Huang, Scott Johnson,Jean-Luc Nagel, Aram Nahidipour, Rishiyur Nikhil, Gajinder Panesar, Deepak Panwar, AntonyPavlov, Klaus Kruse Pedersen, Ken Pettit, Joe Rahmeh, Gavin Stark, Wesley Terpstra, Jan-Willemvan de Waerdt, Stefan Wallentowitz, Ray Van De Walker, Andrew Waterman, Andy Wright, andBryan Terminology.

2 About This Document .. Definition Format .. Name (shortname, at 0x123) .. Background .. Supported Features ..32 System Overview53 Debug Module (DM) Debug Module Interface (DMI) .. Reset Control .. Selecting Harts .. a Single Hart .. Multiple Harts .. Hart States .. Run Control .. Abstract Commands .. 11iiiRISC-V External Debug Support Version Command Listing .. Register .. Access .. Memory .. Program Buffer .. Overview of States .. System Bus Access .. Minimally Intrusive Debugging .. Security .. Debug Module Registers .. Debug Module Status (dmstatus, at 0x11) .. Debug Module Control (dmcontrol, at 0x10) .. Hart Info (hartinfo, at 0x12).

3 Hart Array Window Select (hawindowsel, at 0x14) .. Hart Array Window (hawindow, at 0x15) .. Abstract Control and Status (abstractcs, at 0x16) .. Abstract Command (command, at 0x17) .. Abstract Command Autoexec (abstractauto, at 0x18) .. Configuration String Pointer 0 (confstrptr0, at 0x19) .. Next Debug Module (nextdm, at 0x1d) .. Abstract Data 0 (data0, at 0x04) .. Program Buffer 0 (progbuf0, at 0x20) .. Authentication Data (authdata, at 0x30) .. Halt Summary 0 (haltsum0, at 0x40) .. Halt Summary 1 (haltsum1, at 0x13) .. Halt Summary 2 (haltsum2, at 0x34) .. Halt Summary 3 (haltsum3, at 0x35) .. System Bus Access Control and Status (sbcs, at 0x38) .. 32 RISC-V External Debug Support Version System Bus Address 31:0 (sbaddress0, at 0x39).

4 System Bus Address 63:32 (sbaddress1, at 0x3a) .. System Bus Address 95:64 (sbaddress2, at 0x3b) .. System Bus Address 127:96 (sbaddress3, at 0x37) .. System Bus Data 31:0 (sbdata0, at 0x3c) .. System Bus Data 63:32 (sbdata1, at 0x3d) .. System Bus Data 95:64 (sbdata2, at 0x3e) .. System Bus Data 127:96 (sbdata3, at 0x3f) .. 384 RISC-V Debug Mode .. Load-Reserved/Store-Conditional Instructions .. Wait for Interrupt Instruction .. Single Step .. Reset .. XLEN .. Core Debug Registers .. Control and Status (dcsr, at 0x7b0) .. PC (dpc, at 0x7b1) .. Scratch Register 0 (dscratch0, at 0x7b2) .. Scratch Register 1 (dscratch1, at 0x7b3) .. Virtual Debug Registers.

5 Level (priv, at virtual) .. 455 Trigger Native M-Mode Triggers .. Trigger Registers .. Select (tselect, at 0x7a0) .. 49ivRISC-V External Debug Support Version Data 1 (tdata1, at 0x7a1) .. Data 2 (tdata2, at 0x7a2) .. Data 3 (tdata3, at 0x7a3) .. Info (tinfo, at 0x7a4) .. Control (tcontrol, at 0x7a5) .. Context (mcontext, at 0x7a8) .. Context (scontext, at 0x7aa) .. Control (mcontrol, at 0x7a1) .. Instruction Count (icount, at 0x7a1) .. Interrupt Trigger (itrigger, at 0x7a1) .. Exception Trigger (etrigger, at 0x7a1) .. Trigger Extra (RV32) (textra32, at 0x7a3) .. Trigger Extra (RV64) (textra64, at 0x7a3) .. 616 Debug Transport Module (DTM) JTAG Debug Transport Module.

6 Background .. DTM Registers .. (at 0x01) .. Control and Status (dtmcs, at 0x10) .. Module Interface Access (dmi, at 0x11) .. (at 0x1f) .. JTAG Connector .. 67A Hardware Abstract Command Based .. Execution Based .. 69B Debugger Implementation71 RISC-V External Debug Support Version Debug Module Interface Access .. Checking for Halted Harts .. Halting .. Running .. Single Step .. Accessing Registers .. Using Abstract Command .. Using Program Buffer .. Reading Memory .. Using System Bus Access .. Using Program Buffer .. Using Abstract Memory Access .. Writing Memory .. Using System Bus Access .. Using Program Buffer.

7 Using Abstract Memory Access .. Triggers .. Handling Exceptions .. Quick Access .. 79C Bug .. Resume ack bit is set after resuming .. not affect Argument Width .. Order of Operations .. Hart reset behavior whenhaltreqis set .. applies when action=0 .. tosvalue.. 81viRISC-V External Debug Support Version Last trigger example .. 81 Index82 List of RISC-V Debug System Overview .. Run/Halt Debug State Machine .. 17viiList of Register Access Abbreviations .. Use of Data Registers .. Meaning ofcmdtype.. Abstract Register Numbers .. System Bus Data Bits .. Debug Module Debug Bus Registers .. Core Debug Registers .. Virtual address in DPC upon Debug Mode Entry.

8 Virtual Core Debug Registers .. Privilege Level Encoding .. Trigger Registers .. Suggested Breakpoint Timings .. JTAG DTM TAP Registers .. MIPI-10 Connector Diagram .. MIPI-20 Connector Diagram .. JTAG Connector Pinout .. 68viiiChapter 1 IntroductionWhen a design progresses from simulation to hardware implementation, a user s control and un-derstanding of the system s current state drops dramatically. To help bring up and Debug low levelsoftware and hardware, it is critical to have good debugging Support built into the hardware. Whena robust OS is running on a core, software can handle many debugging tasks. However, in manyscenarios, hardware Support is document outlines a standard architecture for External Debug Support on RISC-V architecture allows a variety of implementations and tradeoffs, which is complementary tothe wide range of RISC-V implementations.

9 At the same time, this specification defines commoninterfaces to allow debugging tools and components to target a variety of platforms based on theRISC-V designers may choose to add additional hardware Debug Support , but this specificationdefines a standard interface for common TerminologyAplatformis a single integrated circuit consisting of one or morecomponents. Some componentsmay be RISC-V cores, while others may have a different function. Typically they will all beconnected to a single system bus. A single RISC-V core contains one or more hardware threads, a hart is its widest supported XLEN, ignoring the current value ContextThis document is written to work with:1. The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version (theISA Spec)12 RISC-V External Debug Support Version The RISC-V Instruction Set Manual, Volume II: privileged Architecture, Version (thePrivileged Spec) VersionsVersion of this document was ratified by the RISC-V Foundation s board.

10 Versions fix releases to that ratified will be forwards and backwards compatible with Version About This StructureThis document contains two parts. The main part of the document is the specification, which isgiven in the numbered sections. The second part of the document is a set of appendices. Theinformation in the appendices is intended to clarify and provide examples, but is not part of theactual Register Definition FormatAll register definitions in this document follow the format shown below. A simple graphic showswhich fields are in the register. The upper and lower bit indices are shown to the top left and topright of each field. The total number of bits in the field are shown below the graphic follows a table which for each field lists its name, description, allowed accesses,and reset value.