SINGLE-CHIP 5-PORT 10/100MBPS SWITCH …

1 RTL8305SC. SINGLE-CHIP 5-PORT 10/100 MBPS SWITCH . controller with dual MII INTERFACES. DataSheet Rev. 02 March 2005. Track ID: JATR-1076-21. RTL8305SC. Datasheet COPYRIGHT. 2005 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. TRADEMARKS. Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners.

2 DISCLAIMER. Realtek provides this document as is , without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. USING THIS DOCUMENT. This document is intended for use by the software engineer when programming for Realtek RTL8305SC. controller chips. Information pertaining to the hardware design of products using these chips is contained in a separate document.

3 Though every effort has been made to assure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process. 5-PORT 10/100 Mbps SINGLE-CHIP dual MII SWITCH controller ii Track ID: JATR-1076-21 Rev. RTL8305SC. Datasheet REVISION HISTORY. Revision Release Date Summary 2004/06/17 First release. 2004/06/30 Removed QoS function IPv6 differentiated services and removed Table 147, page 113.

4 Revised LEDMODE[1:0]=00, in Table 4, page 14, Table 7, page 20, Table 19, page 30, and Table 69, page 59. Changed four combinations of LED mode to three combinations of LED display mode, page 3. 2005/03/02 Corrected section PHY 2 Register 23: Port 2 Control Register 1 to Global Option 1. Register , page 71. Revised pull low resister to 1k ohm, Table 5, page 16. Revised PHY register in Table 64, page 55. Changed Table 139's name from PHY 0 to PHY 5, page 87. Changed Table 140's name from PHY 8 to PHY 5, page 88. Add P4 PHY_MODE select, in Table 143, page 103. Corrected Pin52 MTXEN/PRXDV/EN_TRUNK to MTXEN/PRXDV, Pin92.

5 LED_ACT[4]/DISFCAUTOOFF to LED_ACT[4], and Pin115 ENAGBACK/LED_DUP[0] to LED_DUP[0], in Figure 2, page 7, and Table 1, page 8. Canceled the description of Pin92 LED_ACT[4]/DISFCAUTOOFF and Pin115. ENAGBACK/LED_DUP[0], section 1, page 2, in Table 9, page 22, and section , page 123. Reserved PHY 0 Register and , in Table 68, page 58. Reserved EEPROM Register , in Table 16, page 28 and Register , Table 17, page 29. Corrected QoS based features, section 2, page 4. Corrected 2SB1188K to 2SB1188 and HVDD18 to DVDD18, in Figure 24, page 132, and Table 151, page 132. Corrected 24LC02 must be to 24LC02 must be , section , page 117.

6 Corrected TTL Input High Voltage to and TTL Input Low Voltage to , section , page 134. Corrected PHY 4 register 18 description, in Table 124, page 81. Add 100 Base-TX TD and RD Differential Output Impedance (return loss) columns and delete 10 Base-TX TD and RD Differential Output Impedance (return loss) columns, in Section AC Characteristics, page 135. 5-PORT 10/100 Mbps SINGLE-CHIP dual MII SWITCH controller iii Track ID: JATR-1076-21 Rev. RTL8305SC. Datasheet Table of Contents 1. GENERAL 2. 3. BLOCK 4. PIN ASSIGNMENTS ..7. 5. PIN DESCRIPTIONS ..9. MEDIA CONNECTION PORT 4 CONFIGURATION PINS.

7 9. PORT 4 MAC CIRCUIT interface PINS ..14. PORT 4 PHY CIRCUIT interface PINS ..16. MISCELLANEOUS PINS ..19. PORT LED PINS ..20. SERIAL EEPROM AND SMI PINS ..22. STRAPPING PINS ..22. PORT STATUS STRAPPING PINS ..24. POWER PINS ..26. 6. EEPROM PORT 0 REGISTERS ..27. Global Control Register0 ..27. Global Control Register1 ..27. Global Control Register2 ..28. Global Control Register3 ..28. Global Control Register4 ..28. Global Control Register5 ..29. Global Control Register6 ..29. Global Control Register7 ..30. Port 0 Control Port 0 Control Port 0 Control Port 0 Control Port 0 Control 4 & VLAN Entry [A].

8 32. PORT 1 REGISTERS ..33. Internal Use Port 1 Control Port 1 Control Port 1 Control Port 1 Control Port 1 Control 4 & VLAN Entry [B]..35. PORT 2 REGISTERS ..36. Internal Use Port 2 Control Port 2 Control Reserved ..37. Port 2 Control 2 & VLAN Entry [C] ..38. PORT 3 REGISTERS ..39. SWITCH MAC Address ..39. Port 3 Control Port 3 Control Reserved ..40. 5-PORT 10/100 Mbps SINGLE-CHIP dual MII SWITCH controller iv Track ID: JATR-1076-21 Rev. RTL8305SC. Datasheet Port 3 Control 2 & VLAN Entry [D] ..40. Internal Use PORT 4 REGISTERS ..42. Port 4 Control Port 4 Control Reserved.

9 43. Port 4 Control 2 & VLAN Entry [E]..43. Internal Use Base VLAN ENTRIES ..44. VLAN Entry [F]..44. VLAN Entry [G] ..45. VLAN Entry [H] ..45. VLAN Entry [I] ..46. VLAN Entry [J] ..46. VLAN Entry [K]..47. VLAN Entry [L] ..47. VLAN Entry [M] ..48. VLAN Entry [N]..48. VLAN Entry [O] ..49. VLAN Entry [P]..49. 7. REGISTER DESCRIPTIONS ..50. PHY 0 REGISTERS ..53. PHY 0 Register 0 for Port 0: Control ..53. PHY 0 Register 1 for Port 0: PHY 0 Register 2 for Port 0: PHY Identifier 1 ..54. PHY 0 Register 3 for Port 0: PHY Identifier 2 ..55. PHY 0 Register 4 for Port 0: Auto-Negotiation Advertisement.

10 55. PHY 0 Register 5 for Port 0: Auto-Negotiation Link Partner Ability ..56. PHY 0 Register 16: Global Control PHY 0 Register 17: Global Control PHY 0 Register 18: Global Control PHY 0 Register 19: Global Control PHY 0 Register 22: Port 0 Control Register PHY 0 Register 24: Port 0 Control Register 1 & VLAN ID [A] Membership ..61. PHY 0 Register 25: Port 0 Control Register 2 & VLAN ID [A] ..61. PHY 0 Register 26: Reserved or VLAN ID [F] PHY 0 Register 27: Reserved or VLAN ID [F]..62. PHY 0 Register 28: Reserved or VLAN ID [K] PHY 0 Register 29: Reserved or VLAN ID [K] ..63.