Software Developer Guide - Xilinx

1 zynq UltraScale+ MPSoCSoftware Developer GuideUG1137 ( ) July 1, 2020 Revision HistoryThe following table shows the revision history for this Summary07/01/2020 Version 10: Platform Management Unit FirmwareUpdated PMU Firmware Build Flags to add a new 12: ResetUpdated RPU Subsystem Restart for RPU only restartsupport E: XilSecure Library Additional H: XilFPGA Library Additional Version Embedded FlowUpdated SDK flows to Vitis Embedded Flow throughout Version 4: Software StackUpdated Multimedia Stack 7: System Boot and ConfigurationUpdated Miscellaneous FunctionsChapter 10: Platform Management Unit FirmwareAdded CSU/PMU Register Access and updated PMUF irmware Build FlagsChapter 11: Power Management FrameworkUpdated Sub-system Power ManagementAdded appendix01/18/2019 Version 2: Programming View of zynq UltraScale+ MPSoCDevicesUpdated Boot Modes and System-Level Protections sectionsChapter 3: Development ToolsAdded Device Tree GeneratorChapter 4: Software StackRemoved XilRSA referencesChapter 8: Security FeaturesUpdated Configuring XMPU RegistersChapter 9: Platform ManagementUpdated Power Management FrameworkChapter 10: Platform Management Unit FirmwareUpdated PMU Firmware Build Flags, FPD WDT, and PMUF irmware Memory Layout and FootprintChapter 12: ResetUpdated Warm Restart with a note about on-chip memory(OCM)Chapter 16: Boot Image CreationRemoved content and updated the chapter with a shortdescription and added a reference to the Bootgen Version 7: System Boot and ConfigurationAdded a note that SHA-2 will be deprecated from with a recommendation to use SHA-3 Chapter 8: Security FeaturesAdded Enhanced RSA Key Revocation SupportChapter 10.

2 Platform Management Unit FirmwareUpdated PMU firmware Signals PLL Lock Errors onPS_ERROR_OUT section and PMU firmware Loading Options05/04/2018 Version 8: Security FeaturesAdded BIF File for Obfuscated Form (Gray) Key Stored ineFUSE and updated deprecation of SHA-2 authenticationRevision HistoryUG1137 ( ) July 1, 2020 UltraScale+ mpsoc : Software Developers Guide 2 Send FeedbackSectionRevision SummaryChapter 12: ResetAdded Warm RestartChapter 16: Boot Image CreationUpdated Boot Image format documentation01/19/2018 Version 5: Software Development FlowUpdated Bare Metal Application DevelopmentChapter 7: System Boot and ConfigurationUpdated Boot Flow and Boot Modes sectionsChapter 8: Security FeaturesUpdated BIF File with Multiple AESKEY FilesChapter 13: High-Speed Bus InterfacesUpdated Ethernet flow figuresChapter 16: Boot Image CreationUpdated example for [fsbl_config] parameter11/15/2017 Version 1: About This GuideUpdated PrerequisitesChapter 2: Programming View of zynq UltraScale+ MPSoCDevicesUpdated Boot Process and Security sectionsChapter 4: Software StackUpdated FreeRTOS Software StackChapter 7: System Boot and ConfigurationAdded FSBL Build Process and Setting FSBL CompilationFlags sections.

3 Updated Boot ModesChapter 8: Security FeaturesUpdated Boot Time SecurityChapter 9: Platform ManagementPlatform Management in PS and PMU Firmware sectionsChapter 10: Platform Management Unit FirmwareAdded new chapterChapter 11: Power Management FrameworkUpdated zynq UltraScale+ mpsoc Power ManagementSoftware Architecture, Using the API for PowerManagement, Sub-system Power Management, and XilPMImplementation Details sectionsChapter 16: Boot Image CreationUpdated BIF File Parameters, Boot Image Format and BootHeader Version 2: Programming View of zynq UltraScale+ MPSoCDevicesAdded Boot ProcessChapter 4: Software StackAdded information about Linux Software stack exceptionlevels 7: System Boot and ConfigurationAdded QSPI24 and QSPI32 Boot Modes, eMMC18 BootMode, JTAG Boot Mode, USB Boot Mode. Updated SettingFSBL Compilation Flags to include 8: Security FeaturesAdded Bitstream Authentication Using External Memory, System Memory Management Unit, A53 MemoryManagement Unit, and R5 Memory Protection Encryption and Authentication 16: Boot Image CreationAdded parameters and descriptions in Table 16-1.

4 AddedBoot Image Format. Added additional bit descriptions inTable Appendixes for OS & Libraries content (AppendixesA-K).12/15/2016 Version 1: About This GuideUpdated IntroductionChapter 7: System Boot and ConfigurationUpdated Boot Modes10/05/2016 Version 2: Programming View of zynq UltraScale+ MPSoCDevicesUpdated Boot Modes and removed Interrupt HistoryUG1137 ( ) July 1, 2020 UltraScale+ mpsoc : Software Developers Guide 3 Send FeedbackSectionRevision SummaryChapter 3: Development ToolsAdded Vivado Design Suite. Modified Supported features inXilinx Software Development Kit. Added a link to theSDK_Download. Replaced PetaLinux figure with table in ArmGNU Tools 4: Software StackAdded FreeRTOS Software StackChapter 5: Software Development FlowRemoved Developing Open Source 6: Software Design ParadigmsAdded Frameworks for Multiprocessor DevelopmentChapter 7: System Boot and ConfigurationModified SD Mode diagram, Figure 7-2.

5 Modified NANDMode diagram Figure 7-4. Removed Keys organization in theCSU and Wake UP Mechanisms. Added Pre-Boot 8: Security FeaturesUpdated chapter and removed Encryption Key Types andKey Registers 9: Platform ManagementAdded Power Management Framework and updated PMUF irmwareDMAR emoved chapterSystem CoherencyRemoved chapterChapter 16: Boot Image CreationAdded new chapter11/18/2015 Version HistoryUG1137 ( ) July 1, 2020 UltraScale+ mpsoc : Software Developers Guide 4 Send FeedbackTable of ContentsRevision 1: About This Audience and Scope of this 2: Programming View of zynq UltraScale+ 13 Hardware Architecture Level Reset and Overview for APU and RPU 3: Development Design 28 Vitis Unified Software 30 Arm GNU Tree Software Development using 4: Software 37 Bare Metal Software Software Software 5: Software Development Metal Application Development Using PetaLinux 48UG1137 ( ) July 1, 2020 UltraScale+ mpsoc .

6 Software Developers Guide 5 Send FeedbackLinux Application Development Using 6: Software Design for Multiprocessor Multiprocessing (SMP)..54 Asymmetric Multiprocessing (AMP)..55 Chapter 7: System Boot and Process Image Boot FPD in Boot FSBL Compilation Build 8: Security Time Authentication Using External Trusted Manager 118 Xilinx Memory Protection Peripheral Protection Memory Management Memory Management Memory Protection 9: Platform Management in Up 126 Platform Management for Management for 10: Platform Management Unit ( ) July 1, 2020 UltraScale+ mpsoc : Software Developers Guide 6 Send FeedbackPMU Firmware Inter-Process Interrupts in PMU 133 PMU Firmware Management (EM) Management (PM) Test Register 152 PMU Firmware Loading Firmware Firmware Memory Layout and 11: Power Management UltraScale+ mpsoc Power Management Management Framework 175 Using the API for Power Implementation 197 Arm Trusted Firmware (ATF).

7 214 PMU 12: 220 Block-Level Processing Unit 221 Real Time Processing Unit Power Domain 222 Warm Use 13: High-Speed Bus 248 USB Ethernet ( ) July 1, 2020 UltraScale+ mpsoc : Software Developers Guide 7 Send FeedbackChapter 14: Clock and Frequency the Peripheral 15: Target Development and 16: Boot Image A: Standalone Library Hardware Abstraction Layer Processor R5 Processor Processor Common A9 Processor A53 32-bit Processor A53 64-bit Processor Boot B: LwIP Library C: XilIsf Library Library 388 Library Parameters in MSS D: XilFFS Library Library API Parameters in MSS E: XilSecure Library 429 XilSecure ( ) July 1, 2020 UltraScale+ mpsoc : Software Developers Guide 8 Send FeedbackAppendix F: XilSkey Library PL UltraScale+ mpsoc BBRAM PS 447 zynq eFUSE PS 449 zynq UltraScale+ mpsoc eFUSE PS 451eFUSE PL Calculation Structure G: XilPM Library zynq UltraScale+ mpsoc Structure H: XilFPGA Library I: XilMailbox Structure J: Additional Resources and Legal Navigator and Design Read: Important Legal 578UG1137 ( ) July 1, 2020 UltraScale+ mpsoc : Software Developers Guide 9 Send FeedbackChapter 1 About This GuideIntroductionThis document provides the Software -centric information required for designing and developingsystem Software and applications for the Xilinx zynq UltraScale+ MPSoCs.

8 TheZynq UltraScale+ mpsoc family has different products, based upon the following systemfeatures: Application processing unit (APU): Dual or Quad-core Arm Cortex -A53 MPCore CPU frequency up to GHz Real-time processing unit (RPU): Dual-core Arm Cortex -R5F MPCore CPU frequency up to 600 MHz Graphics processing unit (GPU): Arm Mali-400 MP2 GPU frequency up to 667 MHz Video codec unit (VCU): Simultaneous Encode and Decode through separate cores high profile level (4Kx2K-60) (HEVC) main, main10 profile, level , high Tier, up to 4Kx2K-60 rate 8 and 10-bit encoding 4:2:0 and 4:2:2 chroma samplingFor more details, see the zynq UltraScale+ mpsoc Product Table and the Product 1: About This GuideUG1137 ( ) July 1, 2020 UltraScale+ mpsoc : Software Developers Guide 10 Send FeedbackIntended Audience and Scope of thisDocumentThe purpose of this Guide is to enable Software developers and system architects to becomefamiliar with: Xilinx Software development tools.

9 Available programming options. Xilinx Software components that include device drivers, middleware stacks, frameworks, andexample applications. Platform management unit firmware (PMU firmware), Arm Trusted Firmware (ATF), OpenAMP,PetaLinux tools, Xen Hypervisor, and other tools developed for the zynq UltraScale+ document assumes that you are: Experienced with embedded Software development Familiar with Armv7 and Armv8 architecture Familiar with Xilinx development tools such as the Vivado Integrated Design Environment(IDE), the Vitis unified Software platform, compilers, debuggers, and operating document includes the following chapters: Chapter 2: Programming View of zynq UltraScale+ mpsoc Devices: Briefly explains thearchitecture of the zynq UltraScale+ mpsoc hardware. Xilinx recommends you to go throughand understand each feature of this chapter. Chapter 3: Development Tools: Provides a brief description about the Xilinx softwaredevelopment tools.

10 This chapter helps you to understand all the available features in thesoftware development tools. It is recommended for Software developers to go through thischapter and understand the procedure involved in building and debugging softwareapplications. Chapter 4: Software Stack : Provides a description of various Software stacks such as baremetal Software , RTOS-based Software and the full-fledged Linux stack provided by Xilinx fordeveloping systems with the zynq UltraScale+ mpsoc device. Chapter 5: Software Development Flow: Walks you through the Software developmentprocess. It also provides a brief description of the APIs and drivers supported in the Linux OSand bare 1: About This GuideUG1137 ( ) July 1, 2020 UltraScale+ mpsoc : Software Developers Guide 11 Send Feedback Chapter 6: Software Design Paradigms: Helps you understand different approaches to developsoftware on the heterogeneous processing systems.