SystemVerilog Versus OpenVera - EDA Direct

1 APPLICATION NOTES ystemVerilog Versus OpenVeraStephen BaileyMentor GraphicsVersion , 28 June inspiration for many of the new language capabilities in SystemVerilog has come from proprietary hardware verification languages (HVL) such as Vera and e, especially the , it is understandable that people may be prone to assume that the assertion and verifi-cation capabilities in SystemVerilog are identical to those of OpenVera . Although there are manysimilarities, the two languages are different. If they were identical, it would be possible to suc-cessfully compile and simulate Vera source code in any simulator that supports course, this is not true, and anyone who believes otherwise will be unpleasantly SystemVerilog differs from OpenVera is the topic of this Assertions Versus OpenVera AssertionsUnless otherwise indicated, in this paper, the terms assertionand assertionsrefer to all directives(assert, assume, and cover).

2 AssertionsInline SpecificationSystemVerilog assertions (SVA) can be placed inline (concurrently or procedurally), or they maybe organized with or within interfaces, modules and, to a limited extent, packages. OpenVeraAssertions (OVA) do not support inline specification of must be packaged inunits (as discussed below). In effect, SystemVerilog supports specification of assertions both inline and in separate only supports the specification of assertions in a separate source SystemVerilog , assertions are defined within module or generate regions as a concurrentstatement. That is, they are located within OVA, the cover directives are located in OVAunits. An OVAunit looks like a Verilog moduleexcept the module/endmodule keywords are replaced by the unit/endunit keywords and the portdeclarations use the Verilog ANSI Versus OpenVera1 BindingOVA requires a binding of a unit to a module in the de-sign.

3 Therefore, each OVA unit used inverification will have one or more bindspecifications. SystemVerilog does not require a bindingbut provides a bind construct to facilitate separation of design from verification. Furthermore,there are differences in the semantics of the differences:SVA:bind2module_or instance block_with_props inst_name ( ports ) ;OVA:bind modulemodule_name : instance_name ( ports ) ;bindinstancesinst1, inst2, .., instN : instance_name ( ports ) ;AssertThere are syntactic differences between SVA and OVA assert directives. The most obvious differenceis the lexical order of the assertion name and the assert keyword. The OVA message, severity, andcategory do not exist in SVA. SVA has an action block that can specify statements on pass or failconditions. Finally, OVAsupports built-in formulae meant for use with formal verification. SVAdoes not support these :<name> : assert( <expression> ) [ <action_block> ] ;OVA:assert<name> : builtin_formula ( <seq_expr> [, message [, severity [, category ]]] ) ;CoverThe syntax between SVAand OVAcover directives is also different.

4 The version of theOpenVera Language Reference Manual: Assertions(dated April 2003) contains no documentationfor a cover directive. However, there is a third-party tool that supports this undocumented the OVA cover directive is not documented in the OpenVera LRM, the information providedbelow is based on the best available information. While accurate, it may not be complete. SVA:<name> : cover property( <sva_sequence> ) [ pass_statement ] ;OVA:cover<name> : ( <ova_sequence> ) ;AssumeThe differences in syntax for the assume directive is similar to that documented above forassert and Versus OpenVera Miscellaneous DirectivesOVA defines restrictand modeldirectives that do not exist for SpecificationBoth SVA and OVA provide for the specification of a sampling event (clock specification).However, the syntax differs between the two :The clock expression is specified in the sequence or property ;@(posedgeclk)ready |=> (ack);endpropertysequencebar;@(posedgesy sclk) a ##1 b ##2 c;endsequenceOVA:The clock specification defines a block (clocked entity) within which sequences are ( logic clk, logic ready, logic ack);clockposedge clk {s_foo : (ifready thenack);}endunitSystemVerilog Versus OpenVera3 Sequence SyntaxThe difference in sequence operator syntax between the two languages is best presented via a comparison table.

5 The differences are not DescriptionSystemVerilogOpenVera AssertionTime/cycle advancement##n#nConsecutive repetitionwith rangeseq[*n]seq[*n:m]seq * [n]seq * [n .. m]Non-consecutive repetitionseq[=n], seq[=n:m]N/AGoto repetitionseq[->n]N/AInfinite (unbounded) range[n:$][ ]Implication (same cycle)Next cycleAntecedent<LHS> |-> <RHS> <LHS> |=> <RHS>if(cond) then<T> [else<F>](else is optional)cond must be boolean conditionSequence conjunction (and)<LHS> and<RHS> <LHS> &&<RHS>Intersection (length-matching and)<LHS> intersect<RHS> <LHS> intersect<RHS>Sequence disjunction (or)<LHS> or<RHS> <LHS> || <RHS>Convert sequence to Boolean<seq>.matchedmatched<seq> )first_matchfirst_match(<seq> )first_match( <seq> )Condition over sequence(cond) throughout<seq>istrue(boolexpr) in<seq>length[int/range] in<seq>Sequence within another sequenceseq withinseqLocal variable assignmentSVAassignment w/in assignment is stmta ##1 (b[->1], var= e)initvar_name = const_value;var_name <= expr;Unconditional match`trueanyTemplates (reusable props)templatename ( params ) : {.}

6 }temp_name inst_name ( params ) ;Loop generationVerilog for generatefor(lcv=expr; end_expr; lcv=incr_expr) { .. }Formula operatorsalways(assertion block)N/AN/AN/Adisableiff(approximate)N/ AN/AN/AN/AN/Aalwayseventuallynext, wnextgloballyiffuntil, wuntilfollowed_bytriggersaccept .. in ..reject .. in ..Multiple-clocked sequencesMultiple @<clk_expr> clauses in sequenceMust use matchedto convert sequence inone clock domain to a Boolean value foruse in another clock Versus OpenVera Predefined/Built-in Functions and TasksThe following table shows the differences in support for various built-in functions and tasks for SystemVerilog and Versus SystemVerilog for Testbench and VerificationVera s syntax is more heavily influenced by C than is SystemVerilog s. This is easily seen inthe use of curly braces {} to denote the beginning and ending of a block in Vera whereasSystemVerilog uses a semicolon ; to denote the end of a declaration, and it uses begin andendxyzkeywords to bracket differences exist in the syntax and semantics between the two BlockSystemVerilog program blocks can have ports and parameters.

7 OpenVera program blocks do nothave an interface defined in this manner. Instead, an interface block is specified to provide theconnection between the OpenVera program block and the design. An OpenVera interface is not the same as a SystemVerilog interface (see section on interfacesbelow).DescriptionSystemVerilo gOpenVera AssertionsPrevious value of a signal$past( expr, clk_ev )past( sig, cycles )Future value of a signalN/Afuture( bit_vec_expr )Procedural sampling$sampled( expr, clk_ev )N/ARising edge$rose( expr, clk_ev )N/AFalling edge$fell( expr, clk_ev )N/ANo event for time$stable( expr, clk_ev )N/ANumber of bits 1 in vector$countones( expr )count( bit_vector_expr )One hot$onehot( expr )N/AOne hot with all 0 allowed$onehot0( expr )N/ACheck for unknowns$isunknown( expr )N/ASystemVerilog Versus OpenVera5 Syntactic Differences in Block SyntaxOpenVera:program <name> {.}

8 } SystemVerilog :program <name> [ ( port-list ) ] ;..endprogramOpenVera Interfaces and SystemVerilog Clocking BlocksOpenVera s interface defines how the Vera testbench connects up with the design. This connectionalso specifies input and output skews relative to a signal (such as a clock). SystemVerilog inter-faces serve a completely different purpose. The SystemVerilog program block can be connecteddirectly to the design (and may use SystemVerilog interfaces to do so). The SystemVerilog clockingblock provides the mechanism by which signal sampling is defined within the requires a bind port specification to bind the Vera program to the design s classes can be declared as extern in a header file. Whereas, classes cannot bedeclared as extern in SystemVerilog . OpenVera class members can be localor class members can be local, public (default), or protected.

9 There is no publickeyword in Applicable Syntactic DifferencesSyntactic constructSystemVerilogOpenVeraBlock declaration (program, task, class, etc.)task foo ;endtasktask foo {}Block begin-end delimitersbeginend{}6 SystemVerilog Versus OpenVera SubprogramsData TypesTypeSystemVerilogOpenVeraInteger 2-stateInteger 4-state64-bit integerSigned integerUnsigned integerintintegerlongintint signedint unsignedinteger (always signed)N/AN/AN/AN/ABit 2-stateBit 4-statebitlogicN/AbitAssociative arrays<elem_type> <arr>[<index-type>];Where:* denotes an unspecified index type<elem_type> <arr>[];(that is, only unspecified index types)System (built-in) tasks(when the same task is defined in both languages)$<taskname>(..)<taskname>(..)Enumerated typesenum[<base-type>] { lit1 [=encoding], lit2, .. }[<obj>];Note: Must combine with typedef to namethe enum <name> = lit1, lit2.

10 ;Packed dataArrays: Location of index rangeStructs: use of packedkeywordClass members via use of the packedkeyword. Can be modified with big_endianand little_endian, bit_normal, andbit_reverse. pack() and unpack() prede-fined and functions, by default, are automatickeyword is required todeclare task as and functions are always passingValue: default : parameters declared as refare passed by : default mechanismReference: parameters declared as varare passed by parameter valuesYesYesOptional parametersNo (Not in the Vera sense)YesDeclaration scopeModule or generate , Verilog name space is by localkeyword to limit statementYesYesDiscarding function resultvoid (func(a, b, c));void = func(a, b, c); SystemVerilog Versus OpenVera7 Preprocessor MacrosMiscellaneousConstraints and WeightingsCapabilitySystemVerilogOpenVer aRandom datarandrandcrandrandcDynamic arraysrand logic [7:0] len;rand integer data[];constraint db { == len; }rand bit [7:0] len;rand integer data[] assoc_sizelen;Set membershipexpinside{ <set> }!