Transcription of SystemVerilog Versus OpenVera - EDA Direct
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SystemVerilog Versus OpenVera - EDA Direct
APPLICATION NOTES ystemVerilog Versus OpenVeraStephen BaileyMentor GraphicsVersion , 28 June inspiration for many of the new language capabilities in SystemVerilog has come from proprietary hardware verification languages (HVL) such as Vera and e, especially the , it is understandable that people may be prone to assume that the assertion and verifi-cation capabilities in SystemVerilog are identical to those of OpenVera . Although there are manysimilarities, the two languages are different. If they were identical, it would be possible to suc-cessfully compile and simulate Vera source code in any simulator that supports course, this is not true, and anyone who believes otherwise will be unpleasantly SystemVerilog differs from OpenVera is the topic of this Assertions Versus OpenVera AssertionsUnless otherwise indicated, in this paper, the terms assertionand assertionsrefer to all directives(assert, assume, and cover).
Introduction The inspiration for many of the new language capabilities in SystemVerilog has come from proprietary hardware verification languages (HVL) such as Vera and e, especially the former. Therefore, it is understandable that people may be prone to assume that the assertion and verifi-
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