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(IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 5, No. 4, 2014 155 | P a g e DUT Verification Through an Efficient and Reusable Environment with Optimum Assertion and Functional Coverage in SystemVerilogDeepika Ahlawat VLSI Group Department of Electrical, Electronics & Communication Engineering, ITM University, Gurgaon, (Haryana), India Neeraj Kr. Shukla VLSI Group Department of Electrical, Electronics & Communication Engineering, ITM University, Gurgaon, (Haryana), India Abstract Verification is the most integral part of chip manufacturing and testing and is as important as the designing. Verification provides with the actual implementation and functionality of a Design under Test (DUT) and checks if it meets the specifications or not. In this paper, a communication protocol has been verified as per the design specifications.
(IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 5, No. 4, 2014 156 | P a g e www.ijacsa.thesai.org 5) SV extends the modeling aspects of Verilog by adding a Direct Programming Interface which allows C, C++, SystemC
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