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TriCore Debugger and Trace - Lauterbach

TriCore Debugger and Trace 1 1989-2018 Lauterbach GmbHTriCore Debugger and TraceTRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents .. ICD In-Circuit Debugger .. Processor Architecture Manuals .. TriCore .. TriCore Debugger and Trace ..1 History ..7 Brief Overview of Documents for New Users ..7 Safety Precautions ..8 Introduction ..9 Available Tools9 Debugger9 On-chip Trace10 Serial Off-chip Trace (AGBT)10 Parallel Off-chip Trace10 Co-Processor Debugging (PCP/GTM)10 Multicore Debugging and Tracing10 Software Installation11 Configuration11 System Overview11 Related Documents12 Demo and Start-up Scripts12 OCDS Levels13

TrOnchip.EXTernal Configure TriCore break on BreakBus event 121 TrOnchip.PERSTOPOUT Route suspend signal to pin 121 TrOnchip.RESet Reset settings for the on-chip trigger unit 121 TrOnchip.SoftWare Configure 'TriCore' break on debug instruction 122 TrOnchip.SusSWitch Enable or disable suspend switch 122

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Transcription of TriCore Debugger and Trace - Lauterbach

1 TriCore Debugger and Trace 1 1989-2018 Lauterbach GmbHTriCore Debugger and TraceTRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents .. ICD In-Circuit Debugger .. Processor Architecture Manuals .. TriCore .. TriCore Debugger and Trace ..1 History ..7 Brief Overview of Documents for New Users ..7 Safety Precautions ..8 Introduction ..9 Available Tools9 Debugger9 On-chip Trace10 Serial Off-chip Trace (AGBT)10 Parallel Off-chip Trace10 Co-Processor Debugging (PCP/GTM)10 Multicore Debugging and Tracing10 Software Installation11 Configuration11 System Overview11 Related Documents12 Demo and Start-up Scripts12 OCDS Levels13 Debugging.

2 14 Single-Core Debugging (AUDO)15 Single-Core Debugging - Quick Start15 Multicore Debugging (AURIX)17 SMP Debugging - Quick Start17 AMP Debugging - Quick Start19 AMP vs. SMP21 Selecting the right AURIX CPU22 Understanding Multicore Startup by Application Code22 About Ambiguous Symbols23 Access Classes24 TriCore Debugger and Trace 2 1989-2018 Lauterbach GmbH Breakpoints25 Software Breakpoints25 On-chip Breakpoints25 Command26 Advanced Breakpoints26 Single Stepping27 Assembler Level27 HLL Level27 Flash28 Onchip Triggers (TrOnchip Window)

3 30 BenchMarkCounter31 Example: Measuring Instructions and Stalls per Clock Cycle31 Example: A-to-B Mode33 Example: Record Counters Periodically34 Watchpins35 AUDO35 AURIX35 Cache Access39 AURIX Devices39 Parallel Usage of a 3rd-Party Tool41 Physical Sharing of the Debug Port41 Debugging an Application with the Memory Protection Unit Enabled43 TriCore and Later43 TriCore and Earlier43 Debugging with MPU Enabled in RAM43 Debugging with MPU Enabled in FLASH44 Debugging through Resets and Power Cycles45 Soft

4 Resets45 Hard Resets46 Power Cycles47 Internal Break Bus (JTAG)49 Cerberus Access Protection49 Troubleshooting50 Errors50 Debugging Optimized Code50 FAQ52 Tracing ..60 On-chip Trace (OCDS-L3)60 Quick Start for Tracing with On-chip Trace (OCDS-L3)60 Supported Features61 Trace Control62 Trace Evaluation62 Impact of the Debugger on FPI Bus Tracing62 TriCore Debugger and Trace 3 1989-2018 Lauterbach GmbH Simple Trace Control63 Examples63 Command Reference.

5 67 PCPS elect PCP trace67 About the BMC Commands67 BMC configuration window67 core clock for cycle counter69 BMC.<counter>.ATOBC ontrol A-to-B mode69 About the Commands70 target configuration70 Debugger according to target topology71 Daisy-chain Example73 TapStates74 core to TRACE32 instance75 BreakPIND efine mapping of break pins76 DAPC onfigure DAP interface77 mapping of break pins77 DAP mode on PORST77 and set USER pins78 target interface79 debug cable interface mode79 DXCPLC onfigure DXCPL80

6 SPD timing for DXCPL80 external watchdog80 PortSHaRingControl sharing of debug port with other tool81 CPU81 CPU access (intrusive)82 the JTAG frequency82 the JTAG port83 memory access (non-intrusive)84 the communication with the CPU85 specific commands86 BREAKFIXE nable workaround for asynchronous breaking86 CBSACCEN<x>Cerberus access protection87 DCFREEZEDo not invalidate cache88 DCREADRead from data cache88 DOWNMODEB ehavior of Down89 DUALPORTRun-time memory access for all windows89 DataTraceEnable data tracing89 ETKD ebugging together with ETK from ETAS90 HeartBeatBug fix to avoid FPI bus conflict90 ICFLUSHF lush instruction cache

7 At 'Go' or 'Step'91 IMASKASMD isable interrupts while single stepping91 TriCore Debugger and Trace 4 1989-2018 Lauterbach GmbH IMASKHLLD isable interrupts while HLL single stepping91 INTSTARTS tart address of interrupt routines92 INTUSEN umber of implemented interrupts92 JTAGENSEQUse JTAG initialization sequence92 KEYCODESet debug interface password93 LBISTLBIST gap handling93 OCDSELOWSet OCDS line to low94 OVCE nable OVERLAY memory access95 PERSTOPE nable global peripheral suspend95 PMILBFIXE nable PMI line buffer invalidation workaround95 PostResetDELAYD elay after RESET is released97 ReadOnlyBlock all write accesses97 RESetBehaviorSet behavior when a reset occurs98 ResetDetectionSet how hard resets are detected98 RESetTMSS tate of TMS line at reset99 SOFTLONGSet 32 bit software breakpoints99 STEPONCHIPStep with onchip breakpoints99 STEPSOFTStep with software breakpoints100 TB1766 FIXBug fix for some TC1766 TriBoards100

8 TRAPSTARTS tart address of trap vectors100 WDTFIXD isables the watchdog on WDTSUSLink the watchdog timer to the suspend bus101 reset102 window102 CPU specific TrOnchip Commands103 break pin of 'BreakBus N'103 break pin of 'BreakBus N'103 <target>Connect break <target> to BreakBus104 <source>Connect break <source> to BreakBus104 <source>105 HaLTEN105 range breakpoint in on-chip resource106 X counter value106 Y counter value106 TriCore break on BreakBus event107 settings for the on-chip trigger unit107 ' TriCore ' break on debug instruction107 or disable suspend switch108 generation of suspend signal108 suspend switch mode108 special targets to the suspend bus109 mode for data breakpoints109 data compression109 TriCore Debugger and Trace 5 1989-2018 Lauterbach GmbH trigger delay (obsolete)

9 110 for external trigger input110 of external trigger input110 mode (obsolete)110 trigger event 0111 trigger event 1112 on-chip trigger window112 trigger source X113 trigger source Y113 Technical Data ..114 JTAG Connector114 Trace Connector116 AMP 40 Connector116 ERF8 22-pin Connector117 Samtec 60 Connector117 Technical Data for Debugger119 Operation Voltage119 Mechanical Dimensions119 Technical Data for Trace120 Operation Frequency120 Operation Voltage120 Mechanical Dimensions121 Support123 Available Tools123 Compilers126 Target Operating Systems127

10 3rd-Party Tool Integrations127 Products129 Product Information129 Order Information131 Appendix ..133 Parallel Off-chip Trace - OCDS-L2 Flow Trace (Analyzer)133 Overview133 Quick Start for Tracing with OCDS-L2 Trace (Analyzer)133 Supported Features134 Version History135 Timestamp Accuracy135 Concurrent Usage of OCDS-L2 Off-chip Trace and OCDS-L3 On-chip Trace136 Simple Trace Control136 Trace Break Signals (OCDS-L2)136 Trace Examples137 Troubleshooting for OCDS-L2 Trace139 No Data in Visible139 TriCore Debugger and Trace 6 1989-2018 Lauterbach GmbH Error Diagnosis139