Unclamped Inductive Switching Rugged MOSFETs For …

1 AN601 vishay SiliconixDocument Number: FaxBack 408-970-56001 Unclamped Inductive Switching Rugged MOSFETs For Rugged EnvironmentsThe evolution of the power MOSFET has resulted in a veryrugged transistor. The semiconductor industry defines thisruggedness as the capability to withstand avalanche currentswhen subjected to Unclamped Inductive Switching . Historically,MOSFET manufacturers chose to quantify ruggedness, notbased principally on individual performance, but rather oncomparative performance with other manufacturers. Siliconixhas optimized the cell structure of power MOSFETs , resultingin a new class of extremely Rugged devices. Today savalanche-rated MOSPOWER FET exhibits a ruggednessthat far exceeds the performance of any power MOSFET ofearlier application note reviews the history of unclampedinductive Switching (UIS) and examines various theoriespertaining to failure.

2 It further identifies what appears to be tworelated mechanisms thermal and bipolar believed to beresponsible for failure during Unclamped Inductive switchingand concludes by recommending how a power MOSFET should be qualified for ruggedness in the data failure modes exist when MOSFETs are subjected to this article, these failure mechanisms are labelled as eitheractive or passive. The first, or active mode, results when theavalanche current forces the parasitic bipolar transistor intoconduction. The second, or passive mode, results when theinstantaneous chip temperature reaches a critical value.[1] Atthis elevated temperature, a mesoplasma * forms within theparasitic npn bipolar transistor and causes catastrophicthermal runaway. In either case, the MOSFET is passive mechanism is, therefore, identified as that failuremode not directly attributed to avalanche and DefinitionsWhenever possible, symbols and definitions established bythe JEDEC Committee, JC-25, are used in this article.

3 To clearup any discrepancies, however, the following list describessymbols used frequently in this peak current reached during avalanchetAVthe time duration of the avalanche phenomenonLthe value of inductanceV(BR)effthe breakdown voltage in avalancheWhat is Unclamped Inductive Switching ?Whenever current through an inductance is quickly turned off,the magnetic field induces a counter electromagnetic force(EMF) that can build up surprisingly high potentials across theswitch. Mechanical switches often have spark-suppressioncircuits to reduce these harmful effects that result when currentis suddenly interrupted. However, when transistors are usedas the switches, the full buildup of this induced potential mayfar exceed the rated breakdown (V(BR)DSS) of the transistor,thus resulting in catastrophic we know the size of the inductor, the amount of current beingswitched, and the speed of the switch, the expected potentialmay be easily calculated asV =L di/dt + VDD(1)whereL =the inductance (H)di/dt=rate of change of current (A/s)VDD=the supply voltage (V)*A mesoplasma, according to Ghandhi, takes the form of a glowing red spot having an average temperature in excess of 650 C and a peak core temperature in excess of 1000 C.

4 This mesoplasma is a result of regenerative thermal FaxBack 408-970-56002 Document Number: 7057215-Feb-94LI+ Test CircuitV(BR)effV(BR)DSSIOVDDtav0 FIGURE Waveform during SwitchingThe classic UIS test circuit in widespread use* is shown inFigure 1. Using this circuit, the energy absorbed by the powerMOSFET may be calculated using(2)E 1 2lo2L V(BR) effV(BR) eff VDD An alternate circuit removes VDD ( , VDD = 0) just prior toswitching the device off, thus eliminating the last term inequation (2).Reviewing the Switching waveform shown in Figure 2, thegate remains on long enough to ramp the current to IO, at whichtime the gate switches off, resulting in an abrupt break in thedrain current. Since the magnetic field of the inductor cannotinstantaneously collapse, a voltage is induced on the drain ofthe MOSFET in accordance with equation (1). This inducedpotential may easily exceed the (avalanche) breakdownvoltage shown on the data sheet.

5 ** During avalanche, thevoltage is clamped at a value of V(BR)eff, and the current storedin the inductor decays linearly from IO to zero. This decay timemay be determined by rearranging equation (1).(3)tAV LloV(BR) effTheories Pertaining to Stress FailuresThe Bipolar Excitation Effect The Active Mode. Theclassic reason for failure when a MOSFET is stressed focuseson the activation and subsequent secondary breakdown of theparasitic bipolar transistor. The intrinsic diode of a DMOS FETis actually the collector-base junction of this parasitictransistor. Whether the stress is a form of dv/dt[2,3] or UIS,current cascading laterally through the p+ region is consideredresponsible for transistor failure when the voltage drop, IORp+,activates this bipolar transistor.[4,5,6] The accepted modelrepresenting this failure mode in the vertical MOSFET structure is offered in Figure initial avalanche current at breakdown is heavilyconcentrated within the MOSFET s inherent Zener diode(afforded by the deep p+ well situated centrally in each cell, asshown in Figure 3).

6 However, as the avalanche currentcontinues to increase, it also spreads across the p/n lateral resistance (Rp) is much greater than the vertical resistance (RB) of the heavily-doped p+ region. Avalanchecurrent concentrated in the p+ (Zener) region does notnormally initiate bipolar action. As the avalanche currentincreases in intensity, it spreads along the p/n barrier, and thescenario follows the classic reasoning. If the avalanchecurrents cascading laterally through the p-doped region(pseudobase region) develop sufficient forward bias across Rpto offset VBE, the normal forward base current, +IB, inconjunction with the beta of the parasitic npn bipolar transistor,will result in a local breakdown voltage equal to BVCEO (whichis approximately half of V(BR)DSS). The resulting mesoplasmacauses thermal runaway and the destruction of the powerMOSFET.

7 *Recommended by JEDEC Committee JC 25.**Avalanche breakdown, V(BR)DSS, offered in the typical data sheet is generally rated at the zero gate voltage drain current (IDSS) of the MOSFET. Avalanche breakdown during UIS (V(BR)eff) is, as shown in Figure 2, at substantially higher drain currents. V(BR)eff is much greater than V(BR) SiliconixDocument Number: FaxBack 408-970-56003 DRAINGATESOURCERbDRAINGATESOURCERPn+RPRP RBPp+epi n IAIASUBSTRATE n+FIGURE Circuit and Cross SectionExamination of Figure 3 suggests that the current necessaryto trigger this series of events might be closely approximatedif both the VBE of the parasitic npn bipolar transistor and Rpwere known.[7] Test patterns available on the semiconductorwafer during manufacture make it possible to examine suchparameters of the parasitic npn bipolar results of VBE, beta, and Rp+ from the testpattern are shown in Figure 4.

8 Because of the deep p+diffusion that forms the Zener structure, the region beneath then+ diffusion where Rp is critical resembles a gradedjunction. This in concert with the dramatic temperature risethat together reduces VBE, raises Rp, and increasesbeta com- complicates any effort to calculate the criticalavalanche current required to excite the parasitic bipolartransistor. Blackburn[8] derived a worst-case calculation;however, the actual performance is substantially better thanpredicted due to second-order s MOSPOWER devices can safely withstand over twotimes the 25 C rated current even at junction temperaturesapproaching 150 C. The active form of failure is no longer theprevalent mode under normal operating conditions. Thelimiting mechanism is now usually a thermal failure caused bythe large temperature increase during Thermal Effect The Passive Mode.

9 During UIS, as theMOSFET is subjected to increasing energy, the internal chiptemperature rises dramatically (equation 4) and is thought togenerate a mesoplasma. Such mesoplasmas (regenerativeheating) lead to the irreversible damage generally associatedwith thermal runaway.[1] * The swiftness of this temperaturerise, see equation (3), tends to make heat sinks irrelevant forUIS /VTemperature ( C)(BETA)(VBE)( /V)FIGURE 4. Parasitic Bipolar Transistor CharacteristicsDuring this avalanche period, as defined by equation (3),energy is dissipated in the device equation (2), resulting in adramatic increase in chip temperature. Blackburn[8] derivedthe following one-dimensional thermal model to calculate themaximum temperature rise, TM.*The increasing temperature during mesoplasma formation results in a decreasing thermal conductivity of silicon (see Figure 5a) which, in turn, results in a further increase in the localized temperature.

10 Thermal runaway is thus FaxBack 408-970-56004 Document Number: 7057215-Feb-94 Po = IOV(BR)effwhere(4)DTM =maximum instantaneoustemperature rise ( C)and TM 2 3 PoKtAV K 2A(rpkc) 2 RpC A=the active chip area (where heat originates)r=the density of siliconk=the thermal conductivity (very temperature dependent (see Figure 5a)c=the specific heat of silicon (alsotemperature dependent (see Figure 1b)R=effective thermal resistance of chip ( C/W)C=effective thermal capacitance of chip (J/ C)Equation (4) can be further manipulated to relate thetemperature rise, TM, to(5) TM 2 3 KloV(BR)effL oV(BR)eff Although V(BR)eff is temperature sensitive, for simplicity weassume it is a constant. Therefore, (6)(7) TMaloL o or TMal3 2oL 1400020040060080010001200100080006004002 00 Temperature (K) ( C)Figure 5a. Conductivity of Silicon vs. Temperature([Physics Review, Vol. 130 (6/ 63)] ( /cm_)Figure 1b.)))