Universal Verification Methodology (UVM) 1.2 User’s Guide

1 Copyright 2011 - 2015 Accellera. All rights Verification Methodology (UVM) User s GuideOctober 8, 2015iiCopyright 2011 - 2015 Accellera. All rights 8, 2015 UVM User s GuideCopyright 2011 - 2015 Accellera Systems Initiative (Accellera). All rights Systems Initiative, 8698 Elk Grove Bldv Suite 1, #114, Elk Grove, CA 95624, USAC opyright 2013 - 2015 Advanced Micro Devices, Inc. All rights Micro Devices (AMD), 7171 Southwest Parkway, Austin, TX 78735 Copyright 2011 - 2015 Cadence Design Systems, Inc. (Cadence). All rights Design Systems, Inc., 2655 Seely Ave., San Jose, CA 95134, 2011 - 2015 Mentor Graphics, Corp. (Mentor). All rights Graphics, Corp.

2 , 8005 SW Boeckman Rd., Wilsonville, OR 97070, USAC opyright 2013 - 2015 NVIDIA CORPORATION. All rights Corporation, 2701 San Tomas Expy, Santa Clara, CA 95050 Copyright 2011 - 2015 Synopsys, Inc. (Synopsys). All rights , Inc., 690 E. Middlefield Rd, Mountain View, CA 94043 This product is licensed under the Apache Software Foundation s Apache License, Version , January 2004. The full license is available at: this Guide offers a set of instructions to perform one or more specific Verification tasks, it should besupplemented by education, experience, and professional judgment. Not all aspects of this Guide may beapplicable in all circumstances. The UVM User s Guide does not necessarily represent the standard ofcare by which the adequacy of a given professional service must be judged nor should this document beapplied without consideration of a project s unique aspects.

3 This Guide has been approved through theAccellera consensus process and serves to increase the awareness of information and approaches inverification Methodology . This Guide may have several recommendations to accomplish the same thing andmay require some judgment to determine the best course of UVM Class Reference represents the foundation used to create the UVM User s Guide . Thisguide is a way to apply the UVM Class Reference, but is not the only way. Accellera believes standardsare an important ingredient to foster innovation and continues to encourage industry innovation based on for improvements to the UVM User s Guide are welcome.

4 They should be sent to the UVMemail 2011 - 2015 Accellera. All rights User s GuideOctober 8, The Typical UVM Testbench UVM Testbench .. UVM Test .. UVM Environment .. UVM Scoreboard .. UVM Agent .. UVM Sequencer .. UVM Sequence .. UVM Driver .. UVM Monitor .. The UVM Class Modeling (TLM) .. TLM, TLM-1, and TLM-1 Basics .. Encapsulation and Hierarchy .. Analysis Communication .. Generic Payload .. Core Interfaces and Ports .. Blocking Transport .. Nonblocking Transport .. Sockets .. Time .. Use Models .. Reusable Verification Modeling Data Items for Generation.

5 Inheritance and Constraint Layering .. Defining Control Fields ( Knobs ) .. Transaction-Level Components .. Creating the Creating the Connecting the Driver and Basic Sequencer and Driver Interaction .. Querying for the Randomized Item .. Fetching Consecutive Randomized Items .. Sending Processed Data back to the Sequencer .. Using TLM-Based Drivers .. Creating the Instantiating Creating the Agent .. Operating Modes .. Connecting Components .. 43ivCopyright 2011 - 2015 Accellera. All rights 8, 2015 UVM User s Creating the Environment .. The Environment Class .. Invoking build_phase.

6 Enabling Scenario Declaring User-Defined Sequences .. Sending Subsequences and Sequence Items .. Starting a Sequence on a Sequencer .. Overriding Sequence Items and Sequences .. Managing End of Implementing Checks and Implementing Checks and Coverage in Classes .. Implementing Checks and Coverage in Interfaces .. Controlling Checks and Coverage .. Verification Components .. Creating a Top-Level Instantiating Verification Components .. Creating Test Classes .. Verification Component Configuration .. Verification Component Configurable Parameters .. Verification Component Configuration Mechanism.

7 Choosing between uvm_resource_db and uvm_config_db .. Using a Configuration Class .. Creating and Selecting a User-Defined Creating the Base Test .. Creating Tests from a Test-Family Base Class .. Test Selection .. Creating Meaningful Constraining Data Items .. Data Item Definitions .. Creating a Test-Specific Frame .. Virtual Creating a Virtual Sequencer .. Creating a Virtual Sequence .. Controlling Other Sequencers .. Connecting a Virtual Sequencer to Subsequencers .. Checking for DUT Creating the Scoreboard .. Adding Exports to uvm_scoreboard .. Requirements of the TLM Implementation.

8 Defining the Action Taken .. Adding the Scoreboard to the Environment .. Summary .. Implementing a Coverage Selecting a Coverage Method .. Implementing a Functional Coverage Model .. Enabling and Disabling Coverage .. the Register Layer Classes .. Usage Model .. 75 Copyright 2011 - 2015 Accellera. All rights User s GuideOctober 8, Sub-register Access .. Mirroring .. Memories are not Mirrored .. Access read / write .. peek / poke .. get / set .. randomize .. update .. mirror .. Concurrent Accesses .. Coverage Predefined Coverage Identifiers .. Controlling Coverage Model Construction and Sampling.

9 Constructing a Register Field Types .. Register Types .. Register File Types .. Memory Types .. Block Types .. Packaging a Register Model .. Maximum Data Size .. Back-door Back-door read/write vs. peek/poke .. Hierarchical HDL Paths .. VPI-based Back-door Access .. User-defined Back-door Access .. Back-door Access for Protected Memories .. Active Monitoring .. Special Registers .. Pre-defined Special Registers .. Unmapped Registers and Memories .. Aliased Registers .. Unimplemented Registers .. RO and WO Registers Sharing the Same Address .. Integrating a Register Model in a Verification Integrating a Register Transaction Adapter.

10 Integrating Bus Sequencers .. Integrating the Register Model with a Bus Monitor .. Randomizing Field Pre-defined Sequences .. Topics .. The uvm_component Base Class .. The Built-In Factory and Overrides .. About the Factory .. Factory Registration .. Component Overrides .. Use Model .. Example .. The Sequence Library .. 137viCopyright 2011 - 2015 Accellera. All rights 8, 2015 UVM User s Advanced Sequence Implementing Complex Scenarios .. Protocol Layering .. Generating the Item or Sequence in Advance .. Executing Sequences and Items on other Sequencers .. Command Line Interface (CLI).