VC707 EVALUATION PLATFORM HW-V7-VC707 D …

1 OfSheetDate:Title:Ver:ABCD1234 DCBA4321 Sheet Size: BRev:Drawn ByTHE DOCUMENTATION IS DISCLOSED TO YOU AS-IS WITH NO WARRANTY OF ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OFCONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES,OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANYMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENTSTATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OFKIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, ORXILINX IS DISCLOSING THIS USER GUIDE, MANUAL, RELEASE NOTE, SCHEMATIC,AND/OR SPECIFICATION (THE DOCUMENTATION ) TO YOU SOLELY FOR USE INTHE DEVELOPMENT OF DESIGNS TO OPERATE WITH XILINX HARDWARE MAY NOT REPRODUCE, DISTRIBUTE, REPUBLISH, DOWNLOAD, DISPLAY, POST,OR TRANSMIT THE DOCUMENTATION IN ANY FORM OR BY ANY MEANS INCLUDING,BUT NOT LIMITED TO, ELECTRONIC, MECHANICAL, PHOTOCOPYING, RECORDING,OR OTHERWISE, WITHOUT THE PRIOR WRITTEN CONSENT OF EXPRESSLY DISCLAIMS ANY LIABILITY ARISING OUT OF YOUR USE OFTHE DOCUMENTATION.

2 XILINX RESERVES THE RIGHT, AT ITS SOLE DISCRETION,TO CHANGE THE DOCUMENTATION WITHOUT NOTICE AT ANY TIME. XILINX ASSUMESNO OBLIGATION TO CORRECT ANY ERRORS CONTAINED IN THE DOCUMENTATION, ORTO ADVISE YOU OF ANY CORRECTIONS OR UPDATES. XILINX EXPRESSLYDISCLAIMS ANY LIABILITY IN CONNECTION WITH TECHNICAL SUPPORT ORASSISTANCE THAT MAY BE PROVIDED TO YOU IN CONNECTION WITH THESCHEM, ROHS COMPLIANTSCH P/N: 0381418 ASSY P/N: 0431663 PCB P/N: 1280586 DISCLAIMERTHE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS")ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICHCAN BE VIEWED AT THIS LIMITED WARRANTYDOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THATIS NOT WITHIN THE SPECIFICATIONS STATED ON THE XILINX DATA SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANYAPPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETYDEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIALRISKS OF DEATH, PERSONAL INJURY OR PROPERTY OR ENVIRONMENTAL DAMAGE("CRITICAL APPLICATIONS").

3 USE OF PRODUCTS IN CRITICAL APPLICATIONS IS ATTHE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALLSPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT : VC707 EVALUATION PLATFORM HW-V7-VC707VC707 EVALUATION PLATFORM (XC7VX485T-FF1761)4-4-2012_15 :Title:Ver:ABCD1234 DCBA4321 Sheet Size: BRev:Drawn ByMECHANICALSSI570 VOLTAGEXLATORS witching ModuleTDITDOTDOTDIU1 FPGATDIJTAG RegulatorSwitching ModuleSwitching ModuleSwitching maxU1 JackSCHEM, ROHS COMPLIANTP arallel FlashSCH P/N: 0381418 ASSY P/N: 0431663 PCB P/N: 1280586 DDR3 SODIMMC onnectorsConnectorPCIe x8 EdgeLEDs, ButtonsPower Controller 2 PWRS witching ModuleSwitching ModuleIIC AddressingVC707 EVALUATION PLATFORMS witchesSFP CageVCCINT @ @ 10 AVCC3V3 @ 10 APower Controller 1 VCC1V5 @ 10 AVCC2V5 @ 10 AMGTAVCC @ 10 AMGTAVTT @ 10 AXADC_VCC @ HeaderDDR3 SODIMMSFP+ jtag HeaderUSB Module or10/100/1000 Ethernet12 VMODE DIPSWITCHUSB UARTMGT SMAD ifferential ClockLCD I/FIIC EEPROMIIC MUXHDMI Video0b00110000b10100000b10100000b101000 0 ADV75120b0111001 SUPPORTS MULTIPLE DEVICESREFER TO BOARD BILL OFPower SupplyVirtex-7 Switching RegulatorIRONWOOD FFG1761 SOCKETMATERIALS ON CONFIRM FPGA PROVIDEDP ower Controller 3 Pages 45-56 VCCAUX_IO @ 10 AVCCBRAM @ 10 AMGTVCCAUX @ 10 AVCC1V8 @ 10 ASwitching ModuleSwitching ModuleSwitching ModuleSwitching ModuleSwitching ModuleSwitching

4 ModuleVCCAUXVADJ @ 10 AVC707 Block HPC2 FMC HPC1 XLATORVOLTAGE0bxxxxx00 FMC HPC 2 FMC HPC 1 FMC HPC1/HPC2 SMA ClockUSB PHY0bxxxxx000b1010100 IIC EEPROMR ecovered ClockPage 21 Pages 22-29 Page 34 Page 32 Page 40 Page 38 Pages 42-43 Page 33 Page 41 Page 36 Page 36 Page 36 Page 20 jtag ConnectorDigilent ModulePage 31 Page 44 Page 39 Page 30 Page 35 Page :26 XXXGNDVCC3V3 GNDDIRVCCBBVCCAGNDAGNDGNDVCC3V3 GRNREDGNDofSheetDate:Title:Ver:ABCD1234 DCBA4321 Sheet Size: BRev:Drawn ByVCCO_0_M10 VCCO_0_T11M1_0_AK10M0_0_AL10M2_0_AJ10 DONE_0_AL11 CFGBVS_0_AH10 PROGRAM_B_0_AJ11 INIT_B_0_AG11 TDI_0_T10 TDO_0_R10 TMS_0_P11 TCK_0_P10 CCLK_0_N10 VCCBATT_0_N11VN_0_AB20VP_0_AA21 VREFP_0_AB21 VREFN_0_AA20 DXP_0_AC21 GNDADC_0_Y20 VCCADC_0_Y21 DXN_0_AC20XC7VX485 TFFG1761 BANK 0 VCCO_13_BB30 VCCO_13_BA33 VCCO_13_AY36 VCCO_13_AV32 VCCO_13_AU35 VCCO_13_AR31

5 VCCO_13_AP34IO_25_VRP_13_AT31IO_L24N_T3_ 13_AR33IO_L24P_T3_13_AP33IO_L23N_T3_13_A P31IO_L23P_T3_13_AN31IO_L22N_T3_13_AR32I O_L22P_T3_13_AP32IO_L21N_T3_DQS_13_AP30I O_L21P_T3_DQS_13_AN30IO_L20N_T3_13_AV31I O_L20P_T3_13_AU31IO_L19N_T3_VREF_13_AT30 IO_L19P_T3_13_AR30IO_L18N_T2_13_AW31IO_L 18P_T2_13_AV30IO_L17N_T2_13_BB31IO_L17P_ T2_13_BA30IO_L16N_T2_13_AY30IO_L16P_T2_1 3_AW30IO_L15N_T2_DQS_13_BA32IO_L15P_T2_D QS_13_BA31IO_L14N_T2_SRCC_13_AY33IO_L14P _T2_SRCC_13_AY32IO_L13N_T2_MRCC_13_AV35I O_L13P_T2_MRCC_13_AV34IO_L12N_T1_MRCC_13 _AW33IO_L12P_T1_MRCC_13_AW32IO_L11N_T1_S RCC_13_AV33IO_L11P_T1_SRCC_13_AU32IO_L10 N_T1_13_AT35IO_L10P_T1_13_AR34IO_L9N_T1_ DQS_13_AU33IO_L9P_T1_DQS_13_AT32IO_L8N_T 1_13_AU36IO_L8P_T1_13_AT36IO_L7N_T1_13_A U34IO_L7P_T1_13_AT34IO_L6N_T0_VREF_13_AY 35IO_L6P_T0_13_AW35IO_L5N_T0_13_BB33IO_L 5P_T0_13_BB32IO_L4N_T0_13_BB36IO_L4P_T0_ 13_BA36IO_L3N_T0_DQS_13_BB34IO_L3P_T0_DQ S_13_BA34IO_L2N_T0_13_AW36IO_L2P_T0_13_A V36IO_L1N_T0_13_BA35IO_L1P_T0_13_AY34IO_ 0_VRN_13_AR35XC7VX485 TFFG1761 BANK 13 SCHEM, ROHS COMPLIANTSCH P/N: 0381418 ASSY P/N: 0431663 PCB P/N: 1280586VC707 EVALUATION PLATFORMFPGA Banks 0,13 FPGA Banks 0, ,35213200MW40 VBAS40-04D6 VCCAUX_IONC21R3062611/10W1%564123U45SC70 _6SN74 AVC1T45125%1 ,3512J52 HDR_1X2 GNDGNDofSheetDate:Title:Ver:ABCD1234 DCBA4321 Sheet Size: BRev:Drawn ByVCCO_14_AN37 VCCO_14_AM30 VCCO_14_AL33 VCCO_14_AK36 VCCO_14_AJ29 VCCO_14_AH32 VCCO_14_AF28IO_25_VRP_14_AG32IO_L24N_T3_ A00_D16_14_AJ28IO_L24P_T3_A01_D17_14_AH2 8IO_L23N_T3_A02_D18_14_AG31IO_L23P_T3_A0 3_D19_14_AF30IO_L22N_T3_A04_D20_14_AK29I O_L22P_T3_A05_D21_14_AK28IO_L21N_T3_DQS_ A06_D22_14_AG29IO_L21P_T3_DQS_14_AF29IO_ L20N_T3_A07_D23_14_AK30IO_L20P_T3_A08_D2 4_14_AJ30IO_L19N_T3A09D25_VREF_14_AH30IO _L19P_T3_A10_D26_14_AH29IO_L18N_T2_A11_D 27_14_AL30IO_L18P_T2_A12_D28_14_AL29IO_L 17N_T2_A13_D29_14_AN33IO_L17P_T2_A14_D30 _14_AM33IO_L16N_T2_A15_D31_14_AM32IO_L16 P_T2_CSI_B_14_AM31IO_L15N_T2_DQSDOUT_CSO B_14_AN34IO_L15P_T2_DQS_RDWR_B_14_AM34IO _L14N_T2_SRCC_14_AL32IO_L14P_T2_SRCC_14_ AL31IO_L13N_T2_MRCC_14_AK32IO_L13P_T2_MR CC_14_AJ32IO_L12N_T1_MRCC_14_AL34IO_L12P _T1_MRCC_14_AK34IO_L11N_T1_SRCC_14_AK33I O_L11P_T1_SRCC_14_AJ33IO_L10N_T1_D15_14_ AJ35IO_L10P_T1_D14_14_AH34IO_L9N_T1_DQS_ D13_14_AJ31IO_L9P_T1_DQS_14_AH31IO_L8N_T 1_D12_14_AL35IO_L8P_T1_D11_14_AK35IO_L7N _T1_D10_14_AH33IO_L7P_T1_D09_14_AG33IO_L 6N_T0_D08_VREF_14_AM37IO_L6P_T0_FCS_B_14 _AL36IO_L5N_T0_D07_14_AP35IO_L5P_T0_D06_ 14_AN35IO_L4N_T0_D05_14_AL37IO_L4P_T0_D0 4_14_AK37IO_L3N_T0_DQS_EMCCLK_14_AP37IO_ L3P_T0_DQS_PUDC_B_14_AP36IO_L2N_T0_D03_1 4_AJ37IO_L2P_T0_D02_14_AJ36IO_L1N_T0_D01 _DIN_14_AN36IO_L1P_T0_D00_MOSI_14_AM36IO _0_VRN_14_AH35XC7VX485 TFFG1761 BANK 14 VCCO_15_BB40 VCCO_15_AW39 VCCO_15_AV42 VCCO_15_AT38 VCCO_15_AR41 VCCO_15_AM40IO_25_VRP_15_AU37IO_L24N_T3_ RS0_15_AW42IO_L24P_T3_RS1_15_AW41IO_L23N _T3_FWE_B_15_BB41IO_L23P_T3_FOE_B_15_BA4 1IO_L22N_T3_A16_15_AV41IO_L22P_T3_A17_15 _AU41IO_L21N_T3_DQS_A18_15_BA42IO_L21P_T 3_DQS_15_AY42IO_L20N_T3_A19_15_AU42IO_L2 0P_T3_A20_15_AT41IO_L19N_T3_A21_VREF_15_ BA40IO_L19P_T3_A22_15_BA39IO_L18N_T2_A23 _15_BB39IO_L18P_T2_A24_15_BB38IO_L17N_T2 _A25_15_AY38IO_L17P_T2_A26_15_AW38IO_L16 N_T2_A27_15_BB37IO_L16P_T2_A28_15_BA37IO _L15N_T2_DQS_ADV_B_15_AY37IO_L15P_T2_DQS _15_AW37IO_L14N_T2_SRCC_15_AY40IO_L14P_T 2_SRCC_15_AY39IO_L13N_T2_MRCC_15_AW40IO_ L13P_T2_MRCC_15_AV40IO_L12N_T1_MRCC_15_A V38IO_L12P_T1_MRCC_15_AU38IO_L11N_T1_SRC C_15_AV39IO_L11P_T1_SRCC_15_AU39IO_L10N_ T1_AD11N_15_AT42IO_L10P_T1_AD11P_15_AR42 IO_L9N_T1_DQS_AD3N_15_AT40IO_L9P_T1_DQS_ AD3P_15_AT39IO_L8N_T1_AD10N_15_AP42IO_L8 P_T1_AD10P_15_AP41IO_L7N_T1_AD2N_15_AR40 IO_L7P_T1_AD2P_15_AP40IO_L6N_T0_VREF_15_ AN39IO_L6P_T0_15_AM39IO_L5N_T0_AD9N_15_A T37IO_L5P_T0_AD9P_15_AR37IO_L4N_T0_15_AN 41IO_L4P_T0_15_AN40IO_L3N_T0_DQS_AD1N_15 _AR39IO_L3P_T0_DQS_AD1P_15_AR38IO_L2N_T0 _AD8N_15_AM42IO_L2P_T0_AD8P_15_AM41IO_L1 N_T0_AD0N_15_AP38IO_L1P_T0_AD0P_15_AN38I O_0_VRN_15_AM38XC7VX485 TFFG1761 BANK 15 SCHEM, ROHS COMPLIANTSCH P/N: 0381418 ASSY P/N: 0431663 PCB P/N: 1280586VC707 EVALUATION PLATFORMFPGA Banks 14, 15 FPGA Banks 14, :26 BFBB40AW39AV42AT38AR41AM40AU37AW42AW41BB 41BA41AV41AU41BA42AY42AU42AT41BA40BA39BB 39BB38AY38AW38BB37BA37AY37AW37AY40AY39AW 40AV40AV38AU38AV39AU39AT42AR42AT40AT39AP 42AP41AR40AP40AN39AM39AT37AR37AN41AN40AR 39AR38AM42AM41AP38AN38AM38U1 SOC_V7_485T_FF1761_IRONSOC_V7_485T_FF176 1_IRONAN37AM30AL33AK36AJ29AH32AF28AG32AJ 28AH28AG31AF30AK29AK28AG29AF29AK30AJ30AH 30AH29AL30AL29AN33AM33AM32AM31AN34AM34AL 32AL31AK32AJ32AL34AK34AK33AJ33AJ35AH34AJ 31AH31AL35AK35AH33AG33AM37AL36AP35AN35AL 37AK37AP37AP36AJ37AJ36AN36AM36AH35U1 SOC_V7_485T_FF1761_IRONSOC_V7_485T_FF176 1_IRON4 VRP_154 VRN_1539 FMC_VADJ_ON_B_LSFMC2_HPC_PRSNT_M2C_B_LS3 9 VCC1V8_FPGAVCC1V8_FPGA211%1 ,36 FLASH_A2435,36 VRP_154ofSheetDate:Title:Ver:ABCD1234 DCBA4321 Sheet Size: BRev:Drawn ByVCCO_16_Y36 VCCO_16_AG35 VCCO_16_AE31 VCCO_16_AD34 VCCO_16_AB30 VCCO_16_AA33IO_25_VRP_16_AB34IO_L24N_T3_ 16_AC29IO_L24P_T3_16_AB29IO_L23N_T3_16_A A30IO_L23P_T3_16_AA29IO_L22N_T3_16_AD30I O_L22P_T3_16_AC30IO_L21N_T3_DQS_16_AA32I O_L21P_T3_DQS_16_AA31IO_L20N_T3_16_AD31I O_L20P_T3_16_AC31IO_L19N_T3_VREF_16_Y33I O_L19P_T3_16_Y32IO_L18N_T2_16_AE30IO_L18 P_T2_16_AE29IO_L17N_T2_16_AE35IO_L17P_T2 _16_AE34IO_L16N_T2_16_AF32IO_L16P_T2_16_ AF31IO_L15N_T2_DQS_16_AE33IO_L15P_T2_DQS _16_AE32IO_L14N_T2_SRCC_16_AD35IO_L14P_T 2_SRCC_16_AC34IO_L13N_T2_MRCC_16_AD33IO_ L13P_T2_MRCC_16_AD32IO_L12N_T1_MRCC_16_A C33IO_L12P_T1_MRCC_16_AB33IO_L11N_T1_SRC C_16_AB32IO_L11P_T1_SRCC_16_AB31IO_L10N_ T1_16_AA35IO_L10P_T1_16_AA34IO_L9N_T1_DQ S_16_AB37IO_L9P_T1_DQS_16_AB36IO_L8N_T1_ 16_AA36IO_L8P_T1_16_Y35IO_L7N_T1_16_AA37 IO_L7P_T1_16_Y37IO_L6N_T0_VREF_16_AH36IO _L6P_T0_16_AG36IO_L5N_T0_16_AC36IO_L5P_T 0_16_AC35IO_L4N_T0_16_AD37IO_L4P_T0_16_A D36IO_L3N_T0_DQS_16_AG34IO_L3P_T0_DQS_16 _AF34IO_L2N_T0_16_AF37IO_L2P_T0_16_AE37I O_L1N_T0_16_AF36IO_L1P_T0_16_AF35IO_0_VR N_16_Y34XC7VX485 TFFG1761 BANK 16 VCCO_17_AJ39 VCCO_17_AH42 VCCO_17_AF38 VCCO_17_AE41 VCCO_17_AC37 VCCO_17_AB40IO_25_VRP_17_AG37IO_L24N_T3_ 17_AK42IO_L24P_T3_17_AJ42IO_L23N_T3_17_A L39IO_L23P_T3_17_AK39IO_L22N_T3_17_AJ41I O_L22P_T3_17_AJ40IO_L21N_T3_DQS_17_AL42I O_L21P_T3_DQS_17_AL41IO_L20N_T3_17_AH41I O_L20P_T3_17_AH40IO_L19N_T3_VREF_17_AL40 IO_L19P_T3_17_AK40IO_L18N_T2_17_AK38IO_L 18P_T2_17_AJ38IO_L17N_T2_17_AH38IO_L17P_ T2_17_AG38IO_L16N_T2_17_AG42IO_L16P_T2_1 7_AF42IO_L15N_T2_DQS_17_AH39IO_L15P_T2_D QS_17_AG39IO_L14N_T2_SRCC_17_AG41IO_L14P _T2_SRCC_17_AF41IO_L13N_T2_MRCC_17_AF40I O_L13P_T2_MRCC_17_AF39IO_L12N_T1_MRCC_17 _AD41IO_L12P_T1_MRCC_17_AD40IO_L11N_T1_S RCC_17_AE40IO_L11P_T1_SRCC_17_AE39IO_L10 N_T1_17_AC41IO_L10P_T1_17_AC40IO_L9N_T1_ DQS_17_AE38IO_L9P_T1_DQS_17_AD38IO_L8N_T 1_17_AE42IO_L8P_T1_17_AD42IO_L7N_T1_17_A C39IO_L7P_T1_17_AC38IO_L6N_T0_VREF_17_AA 41IO_L6P_T0_17_AA40IO_L5N_T0_17_AB39IO_L 5P_T0_17_AB38IO_L4N_T0_17_AA42IO_L4P_T0_ 17_Y42IO_L3N_T0_DQS_17_AA39IO_L3P_T0_DQS _17_Y39IO_L2N_T0_17_Y40IO_L2P_T0_17_W40I O_L1N_T0_17_AB42IO_L1P_T0_17_AB41IO_0_VR N_17_Y38XC7VX485 TFFG1761 BANK 17 SCHEM, ROHS COMPLIANTSCH P/N: 0381418 ASSY P/N: 0431663 PCB P/N: 1280586VC707 EVALUATION PLATFORMFPGA Banks 16, 17 FPGA Banks 16, 17BF4-4-2012_15 :Title:Ver:ABCD1234 DCBA4321 Sheet Size: BRev:Drawn ByVCCO_18_W39 VCCO_18_V42 VCCO_18_V32 VCCO_18_U35 VCCO_18_T38 VCCO_18_P34IO_25_VRP_18_W35IO_L24N_T3_18 _U42IO_L24P_T3_18_V41IO_L23N_T3_18_V38IO _L23P_T3_18_W38IO_L22N_T3_18_T42IO_L22P_ T3_18_U41IO_L21N_T3_DQS_18_W42IO_L21P_T3 _DQS_18_W41IO_L20N_T3_18_T41IO_L20P_T3_1 8_T40IO_L