Vertical Diffusion and CVD Tool for Next …

1 Vertical Diffusion and CVD tool for next - generation Semiconductor devices 88 Vertical Diffusion and CVD tool for next -generationSemiconductor DevicesOVERVIEW: In regard to recent patterns in semiconductor fabrication, twofeatures are clear: mass production of a few product varieties, such asDRAMs and MPUs, or small amount production of many product varieties,such as system LSIs. From now onwards, however, demands for shorteningthe fabrication period will grow. In the case of large batches (processing100 to 125 wafers), the standby time needed for output adjustment getslonger, thereby lengthening the fabrication period significantly.

2 Moreover,on top of increases in gas generation and power consumption, it is also aproblem that the quantity of dummy wafers consumed in making up forseveral defective wafers also increases, and the CoO rises dramatically. Inresponse to these challenges, aiming at higher productivity, Hitachi KokusaiElectric Inc. has developed a Vertical -type Diffusion and CVD tool called QUIXACE for handling quick turnaround time with good processperformance at high throughput. With this tool , we will further contributeto improving the production of semiconductor ShimadaMitsuhiro HiranoTakahiro MaedaJie WangINTRODUCTIONAS for the recent trend concerning semiconductorfabrication, the shortening of fabrication work periodsfor mass production of a few product varieties, suchas DRAMs (dynamic random access memories),MPUs (microprocessing units), and flash memories,is being strongly promoted.

3 In line with this trend,Hitachi Kokusai Electric Inc. has developed andcommercialized a new tool called QUIXACE incorporating QTAT (quick turnaround time)technology for shortening the cycle time ofconventional equipment for handling 300-mm-diameter wafers (see Fig. 1). Moreover, by applyingthe QTAT technology to its unique vacuum load-lockequipment and creating a series of QUIXACE units,it is possible to improve productivity, and QUIXACE-L/L for handling applications that require interfacecontrol (such as controlling oxygen atmosphere andwater concentration) was developed and is currentlybeing 1 CVD (chemical vapordeposition)/ Vertical -diffusionAppar atus QUIXACE for next - generation Kokusai Electric Inc.

4 Hasdeveloped QUIXACE based onits amassed extendible high-cleanliness technologies (organicand metallic contaminationreduction) for next -generationdevices and oxidation- Diffusion andgas-phase-reaction technologies for fulfilling the need for flexibilityand high throughput covering smalllots up to large lots of 50 to of QUIXACE High throughput High-precision temperature control High-grade processHitachi Review Vol. 55 (2006), No. 2 89contamination regards the equipment market for processing300-mm wafers, along with variation in devicestructure and handling new materials such as low-kand high-k dielectrics, the transition to single waferprocessing machine that can suppress impurities at thewafer boundary is predicted.

5 On the other hand,reduction of organic and metallic contamination in avertical-type machine and establishment of high-cleanliness techniques for the wafer boundary havemade it possible for a high-productivity Vertical -typeQUIXACE to also handle these addition, by handling rapid increases anddecreases in temperature, QUIXACE decreasesthermal budget, thereby curtailing the advantage of asingle wafer processing CONCEPT BEHINDQUIXACEF eatures of QUIXACEBy applying QTAT technology to our conventionalsuccessfully performing large-batch tool (forprocessing a maximum of 125 wafers) and mini-batchtool (less than 50 wafers)

6 To create a series of machines,we have developed QUIXACE for meeting varioususer needs up to production conditions such asatmospheric control and number of processed utilizing the following main features In the rest of this paper, the development conceptbehind the QUIXACE series is explained, and theperformance and advantages of this series of tools REGARDING SEMICONDUCTORFABRICATION EQUIPMENTIn regards to semiconductor devices beyond the90- and 65-nm technology nodes, along with scaling-down and mass integration, high-reliability and high-grade wafer-processing technologies are being soughtafter.(1) As for device structure, efforts aimed at variousconfigurations such as multi-electrodes are beingmade, and development of deposition systems that canhandle these processes is thus becoming necessary (seeFig.)

7 2).In addition to introduction of strained-silicon andSOI (silicon-on-insulator) techniques, high-k (high-dielectric constant) materials for lowering leakagecurrent of gate insulator films are being , to reduce contact resistance of gateelectrodes, the demands for reducing impurities on awafer surface (boundary) are growing stronger yearby year (see Fig. 3).In the case of high-end processing, to reduceconduction faults in copper interconnections, it isnecessary to reduce minute foreign bodies and voids that is, suppress natural oxidation and reduceFig. 2 Structure of Semiconductor example structure of a logic system LSI device is 3 Requirement Trend Regarding contamination level of wafer surface, whichinfluences device characteristics, is regarding improvement of semi-conductor device characteristicsSelective epitaxy Carrier-mobility improvement Contact-resistance loweringGate electrode Contact-resistance loweringCopper annealing Copper-void suppressionSiO2 SiO2 SiO2 SiO2 CuSiO2 Base metal (tungsten interconnection)Selective epitaxyGate electrode (poly-silicon)Cu/low-k annealing200320042005200620072008 Source.

8 ITRS 2004 (1)45 nm65 nm90 nodeGOI surface metalconcentration(E10 atoms/cm2)Other surface metalconcentration(E10 atoms/cm2)Interface carbonconcentration(E13 atoms/cm2)Interface oxygenconcentration(E13 atoms/cm2)With scaling-down (to the 45-nm node), cleanliness improvement and interface-control techniques must be established.(2007 desired value) Interface carbon concentration< (atoms/cm2) Interface oxygen concentration< (atoms/cm2) Vertical Diffusion and CVD tool for next - generation Semiconductor devices 90(1) high-precision temperature control,(2) high-grade processing,(3) cleaning technology, and(4) high-speed transfer technology QUIXACE dramatically reduces processing timeand accomplishes good process of QUIXACE-L/LFor film deployment of a load-lock device, copperannealing, gate electrode (poly-silicon), and selectiveEpi (epitaxial) are available.

9 As a result, a load-lockdevice QUIXACE-L/L featuring supremetechnologies such as cleaning and interface-impurityreduction was added to the the main features of QUIXACE-L/L are:(1) cleanliness-assuring technology,(2) elimination and control of natural oxide films, and(3) low energy consumption,it can be applied to high-grade wafer processing ofthe next LineupTypical semiconductor fabrication processes andthe features of the corresponding machines are listedin Table 1. Adding to a conventional oxidation/ Diffusion CVD (chemical vapor deposition) unit, theQUIXACE lineup was developed for handling next - generation devices by providing ALD (atomic layerdeposition)

10 And selective epitaxial SiGe the situation of widely diversifiedspecifications required for machines such as a batchALD unit capable of film processing at the atomiclevel, a high-temperature-annealing unit, and a batchepitaxial-SiGe processing according to applicabledevices, a lineup for handling production of variousdevices was created by standardizing a platform ofmachines covering options for handling AND ADVANTAGES OFQUIXACEThe basic performance of QUIXACE is listed inTable Temperature-control TechniqueAchieving stress reduction and oxidation sup-pression for wafers generally involves a sequence forcharging a reactor with a boat at low temperature.