Video and Image Processing Suite User Guide - …

1 Video and Image Processing SuiteUser GuideUpdated for Intel Quartus Prime Design Suite : FeedbackUG-VIPSUITE | document on the web: PDF | HTMLC ontents1. About the Video and Image Processing Release Device Family In-System Performance and Resource Stall Behavior and Error Avalon Streaming Avalon-ST Video Configuration Avalon-ST Video Packet Avalon-ST Video Control Avalon-ST Video Video Avalon-ST Video User Avalon-ST Video Avalon-ST Video Error 283. Clocked Video Embedded Synchronization Format: Clocked Video Embedded Synchronization Format: Clocked Video Input .. Separate Synchronization Video Locked Clocked Video and 4:2:0 Chroma 334. VIP Run-Time 375. Getting IP Catalog and VIP Parameter Specifying IP Core Parameters and Installing and Licensing IP Intel FPGA IP Evaluation VIP Connectivity Avalon-ST Color Space Interfacing with High-Definition Multimedia Interface (HDMI).

2 Interfacing with Interfacing with Serial Digital Interface (SDI).. Unsupported SDI 12G-SDI ..527. Clocked Video Interface Supported Features for Clocked Video Output II Control Clocked Video Input IP Format Format Detection in Clocked Video Input Clocked Video Output IP Video Clocked Video Output II Latency and Image Processing Suite User GuideSend Generator Underflow and Timing Handling Ancillary Modules for Clocked Video Input II IP Clocked Video Input II Signals, Parameters, and Clocked Video Input II Interface Clocked Video Input II Parameter Clocked Video Input II Control Clocked Video Output II Signals, Parameters, and Clocked Video Output II Interface Clocked Video Output II Parameter Clocked Video Output II Control 798. 2D FIR II IP 2D FIR filter 2D FIR filter 2D FIR Coefficient 2D FIR filter No Horizontal Vertical Horizontal and Vertical Diagonal Result to Output Data Type Edge-Adaptive Sharpen Edge 2D FIR filter Parameter 2D FIR filter Control Mixer II IP Alpha Mixer II Parameter Mixer II Control Layer Low-Latency 10010.

3 Clipper II IP Clipper II Parameter Clipper II Control Color Plane Sequencer II IP Combining Color Rearranging Color Splitting and Handling of Subsampled Handling of Non- Image Avalon-ST Color Plane Sequencer Parameter FeedbackVideo and Image Processing Suite User Guide312. Color Space Converter II IP Input and Output Data Color Space Predefined Result of Output Data Type Color Space Converter Parameter Color Space Conversion Control Chroma Resampler II IP Chroma Resampler Nearest Chroma Resampler Parameter Chroma Resampler Control 12214. Control Synchronizer IP Using the Control Synchronizer IP Control Synchronizer Parameter Control Synchronizer Control Deinterlacer II IP Deinterlacing Algorithm Deinterlacing Vertical Interpolation (Bob).. Field Weaving (Weave).. Motion Motion Adaptive High Quality (Sobel Edge Interpolation).

4 Run-time Pass-Through Mode for Progressive Cadence Detection (Motion Adaptive Deinterlacing Only).. Avalon-MM Interface to Motion Adaptive Mode Bandwidth Requirements .. Avalon-ST Video 4K Video Passthrough Support .. Approach Approach Behavior When Unexpected Fields are Handling of Avalon-ST Video Control Deinterlacer II Parameter Deinterlacing Control Scene Change Motion Multiplier Tuning Motion Shift and Motion Scale Frame Buffer II IP Double Triple Locked Frame Rate Converting Frame Handling of Avalon-ST Video Control Packets and User Frame Buffer Parameter and Image Processing Suite User GuideSend Frame Buffer Application Frame Buffer Control Frame Writer Only Frame Reader Only Memory Map for Frame Reader or Writer Gamma Corrector II IP Gamma Corrector Parameter Gamma Corrector Control Configurable Guard Bands IP Guard Bands Parameter Configurable Guard Bands Control Interlacer II IP Interlacer Parameter Interlacer Control 17420.

5 Scaler II IP Nearest Neighbor Bilinear Bilinear Algorithmic Polyphase and Bicubic Polyphase Algorithmic Choosing and Loading Edge-Adaptive Scaling Scaler II Parameter Scaler II Control Switch II IP Switch II Parameter Switch II Control 18922. Test Pattern Generator II IP Test Color Grayscale Black and White SDI Uniform Output Subsampling and Color Generation of Avalon-ST Video Control Packets and Run-Time Test Pattern Generator II Parameter Test Pattern Generator II Control Trace System IP Trace System Parameter Trace System Operating the Trace System from System Loading the Project and Connecting to the Trace Within System TCL Shell FeedbackVideo and Image Processing Suite User Guide524. Warp Lite Intel FPGA Warp Lite IP Release About Image About the Warp Lite Intel FPGA Warp Definition Resampling and Operating the Warp Lite Warp Lite IP Warp Lite IP Control Registers' Warp Lite IP Line Line Store RAM Buffer Ingress and Egress Warp Lite IP Avalon-ST Video Stream Cleaner IP Avalon-ST Video Repairing Non-Ideal and Error Avalon-ST Video Stream Cleaner Parameter Avalon-ST Video Stream Cleaner Control Avalon-ST Video Monitor IP Packet Monitor Avalon-ST Video Monitor Parameter Avalon-ST Video Monitor Control VIP IP Core Software HAL Device Drivers for Nios II Security Using Avalon-ST Video Monitor Debug Configuring Memory Video and Image Processing Suite User Guide Document Revision History for the Video and Image Processing Suite User Avalon-ST Video Verification IP Avalon-ST Video Class Example Generating the

6 Testbench Running the Test in Intel Quartus Prime Standard Running the Test in Intel Quartus Prime Pro Viewing the Video Verification Constrained Random Complete Class c_av_st_video_control .. c_av_st_video_data .. c_av_st_video_file_io .. c_av_st_video_item .. c_av_st_video_source_sink_base ..263 ContentsVideo and Image Processing Suite User GuideSend c_av_st_video_sink_bfm_ SINK .. c_av_st_video_source_bfm_ SOURCE .. c_av_st_video_user_packet .. c_pixel .. av_mm_master_bfm_` av_mm_slave_bfm_` Data FeedbackVideo and Image Processing Suite User Guide71. About the Video and Image Processing SuiteThe Intel Video and Image Processing (VIP) Suite is available in the DSP library ofthe Intel Quartus Prime software. You can configure the IPs to the required numberof bits per symbols, symbols per pixel, symbols in sequence or parallel, and pixels VIP Suite offers the following IPs.

7 2D FIR II Intel FPGA IP Avalon-ST Video Monitor Intel FPGA IP (Available only in Platform Designer(Standard) edition) Avalon-ST Video Stream Cleaner Intel FPGA IP Chroma Resampler II Intel FPGA IP Clipper II Intel FPGA IP Clocked Video Input II Intel FPGA IP Clocked Video Output II Intel FPGA IP Color Plane Sequencer II Intel FPGA IP Color Space Converter II Intel FPGA IP Configurable Guard Bands Intel FPGA IP Control Synchronizer Intel FPGA IP (Available only in Platform Designer (Standard)edition) Deinterlacer II Intel FPGA IP Frame Buffer II Intel FPGA IP Gamma Corrector II Intel FPGA IP Interlacer II Intel FPGA IP Mixer II Intel FPGA IP Scaler II Intel FPGA IP Switch II Intel FPGA IP Test Pattern Generator II Intel FPGA IP Trace System Intel FPGA IP (Available only in Platform Designer (Standard)edition) Warp Lite IPThese IPs transmit and receive Video according to the Avalon streaming videostandard.

8 Most IPs receive and transmit Video data according to the same Avalonstreaming Video configuration, but some explicitly convert from one Avalon streamingvideo configuration to another. For example, you can use the Color Plane Sequencer IIIP to convert from 1 pixel in parallel to | FeedbackIntel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel.

9 Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of :2015 RegisteredAll VIP IPs require even frame widths when using 4:2:2 data; odd frame widths createunpredictable results or distorted images. The Clipper II IP requires even clip startoffsets and the Mixer II IP requires even offsets when using 4:2:2 signal names are standard Avalon streaming signals, and so by default, notenumerated. Some IPs may have additional IPs in the VIP Suite support pixels in parallel, with the exception of ControlSynchronizer, and Avalon-ST Video Monitor IP. Most of the IPs support 8 pixels inparallel and 8K and Maximum Supported X and Y ResolutionsVIP IP CoresMinimum Input and OutputResolution in Pixels (Width Height)Maximum Input and OutputResolution in Pixels (Width Height)Clocked Video Input II32 328192 8192 Clocked Video Output II32 328192 8192 Control Synchronizer32 321920 1080 Deinterlacer II32 324096 2160 (1)Warp Lite IP128 1281920 1080 Other IP32 328192 8192 Related InformationVideo and Image Processing Suite User Guide Archives on page 230 Provides a list of user guides for previous versions of the Video and ImageProcessing Suite IP Release InformationRelease information for the Video and Image Processing FPGA IP versions match the Intel Quartus Prime Design Suite software versionsuntil Starting in Intel Quartus Prime Design Suite software version , IntelFPGA IP has a new versioning Intel FPGA IP version ( )

10 Number can change with each Intel Quartus Primesoftware version. A change in: X indicates a major revision of the IP. If you update the Intel Quartus Primesoftware, you must regenerate the IP. Y indicates the IP includes new features. Regenerate your IP to include these newfeatures. Z indicates the IP includes minor changes. Regenerate your IP to include thesechanges.(1)Deinterlacer II can pass through progressive Video up to a maximum resolution of 4096 About the Video and Image Processing SuiteUG-VIPSUITE | FeedbackVideo and Image Processing Suite User Guide9 Table DateDecember 2019 Ordering CodeIPS- Video ( Video and Image Processing Suite )Intel verifies that the current version of the Intel Quartus Prime software compiles theprevious version of each IP core, if this IP core was included in the previous reports any exceptions to this verification in the Intel FPGA IP Release does not verify compilation with IP core versions older than the previous Information Intel FPGA IP Library Release Notes Errata for VIP Suite in the Knowledge Device Family SupportTable Family SupportThe table lists the device support information for the Video and Image Processing Suite IP cores.