Transcription of Xilinx Constraints Guide (UG625)
1 ConstraintsGuideUG625( )April1,2013 This document applies to the following software versions: ISE Design Suite through document applies to the following software versions: ISE Design Suite through document applies to the following software versions: ISE Design Suite through document applies to the following software versions: ISE Design Suite through information relating to ISE Design Suite timing Constraints , see the Timing Closure User GuideFor information relating to ISE Design Suite timing Constraints , see the Timing Closure User GuideFor information relating to ISE Design Suite timing Constraints , see the Timing Closure User GuideFor information relating to ISE Design Suite timing Constraints , see the Timing Closure User Guide UG612.
2 UG612 . UG612 . UG612 .NoticeofDisclaimerTheinformationdisclos edtoyouhereunder(the"Materials") :(1)Materialsaremadeavailable"ASIS"andwi thallfaults,XilinxherebyDISCLAIMSALLWARR ANTIESANDCONDITIONS,EXPRESS,IMPLIED,ORST ATUTORY,INCLUDINGBUTNOTLIMITEDTOWARRANTI ESOFMERCHANTABILITY,NON-INFRINGEMENT,ORF ITNESSFORANYPARTICULARPURPOSE;and(2)Xili nxshallnotbeliable(whetherincontractorto rt,includingnegligence,orunderanyotherth eoryofliability)foranylossordamageofanyk indornaturerelatedto,arisingunder,orinco nnectionwith,theMaterials(includingyouru seoftheMaterials),includingforanydirect, indirect,special,incidental,orconsequent iallossordamage(includinglossofdata,prof its,goodwill,oranytypeoflossordamagesuff eredasaresultofanyactionbroughtbyathirdp arty) ,modify,distribute.
3 YouassumesoleriskandliabilityforuseofXil inxproductsinCriticalApplications: #critapps. ,theXilinxlogo,Artix,ISE,Kintex,Spartan, Virtex,Vivado,Zynq, , (VCCOSENSEMODE)constraint01/18 MovedtimingconstraintsmaterialtotheTimin gClosureUserGuide(UG612). Removedsentence TNM_NETisapropertynormallyusedinconjunct ionwithanHDLdesigntotagaspecificnet. RemovedreferencetoFSMS tyle(FSM_STYLE) ,Spartan-6,and7 SeriesDevices(UG687). CorrectedsyntaxforTimingGroup(TIMEGRP) TheRISINGandFALLING keywordsmayalsobeusedwithTNM. AddedDIFF_TERM supportforVirtex (VCCOSENSEMODE) (Pullup)constraint,addedinformationthatN GDB uildignoresthefollowing: DEFAULTKEEPER=FALSE DEFAULTPULLUP=FALSE DEFAULTPULLDOWN= ( )April1,2013 DateVersionRevisionForIODELAY_GROUP(IODE LAYG roup)constraint,addedinformationunderLim itationswithLOCandArchitectureSupportFor AreaGroup(AREA_GROUP)constraint, (ConfigurationMode)constraint, (BEL)constraint, ( )April1, (UCF).
4 (PCF)..31 NetlistConstraintsFile(NCF).. (XCF).. ( )April1,2013 Send ( )April1, (LOC).. (RLOC).. ( )April1,2013 Send ( )April1, ( )April1,2013 Send ,seetheTimingClosureUserGuide(UG612). ,certainlanguageconstructsusethetermsatt ributeanddirectiveinsimilar,butnotidenti cal, : Genericmaps(VHDL) Defparamsorinlineparameterpassedwhileins tantiatingtheprimitivecomponent(Verilog) INITonaLUT4component ,placement, (UCF).Theymayalsobeplacedin: TheHardwareDescriptionLanguage(HDL)code ( )April1, FeedbackChapter1:ConstraintTypesImplemen tationConstraintsExamples Location(LOC)(placement) PERIOD(timing) ( )April1,2013 Send FeedbackChapter1:ConstraintTypesCPLDF itterThefollowingconstraintsapplytoCPLD devices:BUFG(CPLD)Collapse(COLLAPSE)Cool CLOCK(COOL_CLK)DataGate(DATA_GATE)Fast(F AST)InputRegisters(INREG)InputOutputStan dard(IOSTANDARD)Keep(KEEP)Keeper(KEEPER) Location(LOC)MaximumProductTerms(MAXPT)N oReduce(NOREDUCE)OffsetIn(OFFSETIN)Offse tOut(OFFSETOUT)OpenDrain(OPEN_DRAIN)Peri od(PERIOD)Prohibit(PROHIBIT)Pullup(PULLU P)PowerMode(PWR_MODE)Registers(REG)Schmi ttTrigger(SCHMITT_TRIGGER)Slow(SLOW)Timi ngGroup(TIMEGRP)TimingSpecifications(TIM ESPEC)TimingName(TNM)TimingSpecification Identifier(TSidentifier)VREFWireAnd(WIRE AND)ConstraintsGuideUG625( )April1, FeedbackChapter1:ConstraintTypesLogicalC onstraintsLogicalconstraintsareconstrain tsthatareattachedtoelementsbeforemapping orfitting.
5 Logicalconstraintshelpadaptdesignperform ancetoexpectedworst-caseconditions. architecture, ,orfit,thedesign. Youcanattachlogicalconstraintsusingattri butesintheinputdesign,whicharewrittenint otheNetlistConstraintsFile(NCF)orNGCnetl ist,orwithaUserConstraintsFile(UCF). Threecategoriesoflogicalconstraintsare: PlacementConstraints RelativeLocationConstraintsForFPGA devices,RelativeLocationconstraints: Grouplogicelementsintodiscretesets. Allowyoutodefinethelocationofanyelementw ithinthesetrelativetootherelementsinthes et,regardlessofeventualplacementintheove ralldesign. ( )April1,2013 Send FeedbackChapter1 Thephysicaldesignisthedesignafterithasbe enmapped. Whenadesignismapped,thelogicalconstraint sin(1)thenetlist,and(2)theUserConstraint sFile(UCF),aretranslatedintophysicalcons traintsthatapplytoaspecificarchitecture.
6 PhysicalconstraintsaredefinedinthePhysic alConstraintsFile(PCF) (PCF)ThePhysicalConstraintsFile(PCF): Isamapper-generatedfile. Containstwosections: SchematicContainsthephysicalconstraintsb asedonthelogicalconstraintsfoundinthenet listandtheUCF. User Canbeusedtoaddanyphysicalconstraints. Xilinx recommendsthatyouplaceuser-generatedcons traintsinaUCF, ( )April1, FeedbackChapter1 AreaGroup BEL BlockName DCIV alue Drive Fast HierarchicalBlockName HierarchicalLookupTableName HUSet IOB InputOutputBlockDelay InputOutputStandard Keep Keeper LookupTableName Map NoDelay Pulldown Pullup RelativeLocation RelativeLocationOrigin RelativeLocationRange SaveNetFlag Slew USet UseRelativeLocation ( )April1,2013 Send FeedbackChapter1:ConstraintTypesPlacemen tConstraintsThissectiondescribestheplace mentconstraintsforeachtypeoflogicelement inFPGA designs,including: Flip-Flop ROM RAM BUFT CLB IOB I/O Edgedecoder GlobalbufferIndividuallogicgatessuchasAN DorORgates: AremappedintoCLBfunctiongeneratorsbefore theconstraintsareread.
7 : HDLsourcecode,or UserConstraintsFile(UCF)Inaconstraintsfi le, , TheUCFandtheNCFarecasesensitive. Identifiernames(namesofobjects,suchasnet names)mustexactlymatchthecaseofthenameas itexistsinthesourcedesignnetlist. Xilinx keywords(suchasLOC,PROHIBIT,RLOC,andBLKN M) : BLKNM HBLKNM HLUTNM LOC LUTNM PROHIBIT RLOC RLOC_ORIGIN RLOC_RANGE XBLKNMC onstraintsGuideUG625( )April1, FeedbackChapter1:ConstraintTypesRelative Location(RLOC)ConstraintsTheRLOC constraintgroupslogicelementsintodiscret esets. Youcandefinethelocationofanyelementwithi nthesetrelativetootherelementsintheset,r egardlessofeventualplacementintheoverall design. Forexample,ifRLOC constraintsareappliedtoagroupofeightflip -flopsorganizedinacolumn,themappermainta insthecolumnarorderandmovestheentiregrou pofflip-flopsasasingleunit.
8 Incontrast, AREA_GROUP BEL LOC LOCATE Prohibit RLOC RLOC_ORIGIN RLOC_RANGE ( )April1,2013 Send FeedbackChapter1:ConstraintTypesRoutingD irectivesRoutingdirectivesinstructPARtop erformspecificoperations. AREA_GROUP CONFIG_MODE LOCK_PINSC onstraintsGuideUG625( )April1, FeedbackChapter1:ConstraintTypesSynthesi sConstraintsSynthesisconstraintsdirectth esynthesistooloptimizationtechniqueforap articulardesignorpieceofHardwareDescript ionLanguage(HDL) , : FROM-TO IOB KEEP MAP MARK_DEBUG OFFSETIN OFFSETOUT PERIOD TIG TNM TNM_NETS ynthesisConstraintDocumentationXSTsynthe sisconstraintsaredocumentedin: XSTUserGuideforVirtex-4,Virtex-5,Spartan -3,andNewerCPLDD evices(UG627) XSTUserGuideforVirtex-6,Spartan-6,and7 SeriesDevices(UG687)Othersynthesisconstr aintsaredocumentedinthesoftwarevendor' ( )April1,2013 Send FeedbackChapter1:ConstraintTypesTimingCo nstraintsTheXilinx (UG612).
9 Thefollowingaretimingconstraintsandassoc iatedgroupingconstraints: AsynchronousRegister Disable Enable FromThruTo FromTo MaximumSkew OffsetIn OffsetOut Period Priority SystemJitter Temperature TimingIgnore TimingGroup TimingSpecifications TimingName TimingNameNet TimingPointSynchronization TimingThruPoints TimingSpecificationIdentifier VoltageConstraintsGuideUG625( )April1, FeedbackChapter1:ConstraintTypesConfigur ationConstraints ConfigurationMode DCIC ascade MCBP erformance Stepping PostCRC PostCRCA ction PostCRCF requency PostCRCINITFlag VCCAUX VREF ( )April1,2013 Send FeedbackChapter2 EntryStrategiesforXilinxConstraintsThisc hapterdiscussesentrystrategiesforXilinx Constraints ,includinghowtouseISE DesignSuiteAREA_GROUPYesYesYesYesYesASYN C_REGYesYesYesYesBELYesYesYesYesBLKNMYes YesYesYesYesBUFG(CPLD)YesYesYesYesYesCLO CK_DEDICATED_ROUTEYesYesCOLLAPSEYesYesYe sYesCOMPGRPYesConstraintsGuideUG625( )April1, FeedbackChapter2:EntryStrategiesforXilin xConstraintsConstraintSche-maticVHDLV erilogNCFUCFC onstr-aintsEditorPCFXCFPlan-AheadPACEFPG AE ditorISE ( )April1,2013 Send FeedbackChapter2.
10 EntryStrategiesforXilinxConstraintsConst raintSche-maticVHDLV erilogNCFUCFC onstr-aintsEditorPCFXCFPlan-AheadPACEFPG AE ditorISE DesignSuiteMAPYesYesYesMARK_DEBUGYesYesY esMAXDELAYYesYesYesYesYesYesYesMAX_FANOU TYesYesYesMAXPTYesYesYesMAXSKEWYesYesYes YesYesYesYesNODELAYYesYesYesYesYesIODELA Y_GROUPYesNOREDUCEYesYesYesYesYesOFFSETI NYesYesYesYesYesYesYesOFFSETOUTYesYesYes YesYesYesYesOPEN_DRAINYesYesYesYesYesPER IODYesYesYesYesYesYesYesYesYesPINYesPOST _CRCYesYesPOST_CRC_ACTIONYesYesPOST_CRC_ FREQYesYesPOST_CRC_INIT_FLAGYesYesPRIORI TYYesYesYesPROHIBITYesYesYesYesYesPULLDO WNYesYesYesYesYesYesYesYesPULLUPYesYesYe sYesYesYesYesYesPWR_MODEYesYesYesYesYesR EGYesYesYesYesYesRLOCYesYesYesYesYesYesR LOC_ORIGINYesYesYesYesYesYesRLOC_RANGEYe sYesYesYesYesYesSAVENETFLAGYesYesYesYesY esSCHMITT_TRIGGERYesYesYesYesYesSLEWYesY esYesYesYesYesYesYesSLOWYesYesYesYesYesY esYesYesSTEPPINGYesSUSPENDYesYesYesYesYe sSYSTEM_JITTERYesYesYesYesYesTEMPERATURE YesYesYesYesTIGYesYesYesYesYesYesYesTIME GRPYesYesYesYesYesYesConstraintsGuideUG6 25( )April1, FeedbackChapter2:EntryStrategiesforXilin xConstraintsConstraintSche-maticVHDLV erilogNCFUCFC onstr-aintsEditorPCFXCFPlan-AheadPACEFPG AE ditorISE DesignSuiteTIMESPECYesYesYesYesYesTNMYes YesYesYesYesTNM_NETYesYesYesYesYesYesTPS YNCYesYesYesTPTHRUYesYesYesYesTSidentifi erYesYesYesYesYesYesU_SETYesYesYesYesYes USE_RLOCYesYesYesYesYesYesUSE_INTERNAL_V REFYesYesYesYesVCCAUXYesYesVCCAUX_IOYesY esYesYesVOLTAGEYesYesYesYesVREFYesYesYes WIREANDYesYesYesYesXBLKNMYesYesYesYesYes SchematicDesignFollowtheserulestoaddXili nx constraintsasattributeswithinasymbolorsc hematicdrawing: Ifaconstraintappliestoanet,additasanattr ibutetothenet.
