Zynq-7000 SoC (Z-7007S, Z-7012S, Z ... - All Programmable

1 DS187 ( ) July 2, Specification1 Copyright 2011 2018 xilinx , Inc. xilinx , the xilinx logo, Zynq, Virtex, Artix, Kintex, Spartan, ISE, Vivado and other designated brands included herein are trademarks of xilinx in the United States and other countries. AMBA, AMBA Designer, ARM, Cortex-A9, CoreSight, Cortex, PrimeCell, ARM Powered, and ARM Connected Partner are trademarks of ARM Ltd. All other trademarks are the property of their respective Zynq -7000 SoCs are available in -3, -2, -1, and -1LI speed grades, with -3 having the highest performance. The -1LI devices can operate at either of two Programmable logic (PL) VCCINT/VCCBRAM voltages, and , and are screened for lower maximum static power. The speed specification of a -1LI device is the same as the -1 speed grade. When operated at PL VCCINT/VCCBRAM = , the -1LI static and dynamic power is reduced. Zynq-7000 device DC and AC characteristics are specified in commercial, extended, industrial and expanded (Q-temp) temperature ranges.

2 Except for the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices are available in the commercial, extended, industrial, or Q-temp temperature supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical available device/package combinations are outlined in: Zynq-7000 SoC Overview (DS190) XA Zynq-7000 SoC Overview (DS188) Defense-grade Zynq-7000Q SoC Overview (DS196)This Zynq-7000 SoC data sheet, which covers the specifications for the XC7Z007S, XC7Z012S, XC7Z014S, XC7Z010, XA7Z010, XC7Z015, XC7Z020, XA7Z020, and XQ7Z020, complements the Zynq-7000 SoC documentation suite available on the xilinx website at Characteristics Zynq-7000 SoC(Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020):DC and AC Switching CharacteristicsDS187 ( ) July 2, 2018 Product SpecificationTable 1.

3 Absolute Maximum Ratings(1)SymbolDescriptionMinMaxUnitsPr ocessing System (PS)VCCPINTPS internal logic supply voltage auxiliary supply voltage PLL supply DDR I/O supply voltage (2)PS MIO I/O supply voltage input reference voltage (2)(3)(4)(5)PS MIO I/O input voltage + DDR I/O input voltage + Logic (PL)VCCINTPL internal supply voltage auxiliary supply voltage supply voltage for the block RAM memories supply voltage for HR I/O banks reference voltage FeedbackZynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)DS187 ( ) July 2, Specification2 VIN(3)(4)(5)I/O input voltage for HR I/O banks + input voltage (when VCCO= ) for VREF and differential I/O standards except TMDS_33(6) VVCCBATTKey memory battery backup supply Transceiver (XC7Z015 Only)VMGTAVCCA nalog supply voltage for the GTP transmitter and receiver circuits supply voltage for the GTP transmitter and receiver termination circuits clock absolute input voltage (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage input current for receiver input pins DC coupled RX termination = floating 14mAIDCIN-MGTAVTTDC input current for receiver input pins DC coupled RX termination = VMGTAVTT 12mAIDCIN-GNDDC input current for receiver input pins DC coupled RX termination = GND output current for transmitter pins DC coupled RX termination = floating 14mAIDCOUT-MGTAVTTDC output current for transmitter pins DC coupled RX termination = VMGTAVTT 12mAXADCVCCADCXADC supply relative to GNDADC reference input relative to GNDADC temperature (ambient) 65150 CTSOLM aximum soldering temperature for Pb/Sn component bodies(7) +220 CMaximum soldering temperature for Pb-free component bodies(7) +260 CTjMaximum junction temperature(7)

4 +125 beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device to both MIO supply banks VCCO_MIO0 and lower absolute voltage specification always I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471) or the Zynq-7000 SoC Technical Reference Manual (UG585). maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table Table 11 for TMDS_33 soldering guidelines and thermal considerations, see the Zynq-7000 SoC Packaging and Pinout Specification (UG865).Table 2:Recommended Operating Conditions(1)(2)SymbolDescriptionMinTypM axUnitsPSVCCPINTPS internal logic supply auxiliary supply PLL DDR I/O supply (3)PS MIO I/O supply voltage for MIO 1.

5 Absolute Maximum Ratings(1) (Cont d)SymbolDescriptionMinMaxUnitsSend FeedbackZynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)DS187 ( ) July 2, Specification3 VPIN(4)PS DDR and MIO I/O input voltage VCCO_DDR+ VCCO_MIO+ (5)PL internal supply -1LI ( ) internal supply auxiliary supply (5)PL block RAM supply -1LI ( ) block RAM supply (6)(7)PL supply voltage for HR I/O (4)I/O input voltage VCCO+ input voltage (when VCCO= ) for VREF and differential I/O standards except TMDS_33(8) (9)Maximum current through any (PS or PL) pin in a powered or unpowered bank when forward biasing the clamp diode 10mAVCCBATT(10)Battery Transceiver (XC7Z015 Only)VMGTAVCC(11)Analog supply voltage for the GTP transmitter and receiver (11)Analog supply voltage for the GTP transmitter and receiver termination supply relative to supplied reference temperature operating range for commercial (C) temperature devices0 85 CJunction temperature operating range for extended (E) temperature devices0 100 CJunction temperature operating range for industrial (I) temperature devices 40 100 CJunction temperature operating range for expanded (Q) temperature devices 40 125 voltages are relative to ground.

6 The PL and PS share a common the design of the power distribution system consult the Zynq-7000 SoC PCB Design Guide (UG933). to both MIO supply banks VCCO_MIO0 and lower absolute voltage specification always and VCCBRAM should be connected to the same data is retained even if VCCO drops to VCCO of , , , , , and at 5%. Table 11 for TMDS_33 total of 200 mA per PS or PL bank should not be VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or Each voltage listed requires the filter circuit described in the 7 Series FPGAs GTP Transceiver User Guide (UG482).Table 2:Recommended Operating Conditions(1)(2) (Cont d)SymbolDescriptionMinTypMaxUnitsSend FeedbackZynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)DS187 ( ) July 2, Specification4 Table 3:DC Characteristics Over Recommended Operating ConditionsSymbolDescriptionMinTyp(1)MaxU nitsVDRINTData retention VCCINT voltage (below which configuration data might be lost) VVDRIData retention VCCAUX voltage (below which configuration data might be lost) VIREFPS_DDR_VREF 0/1, PS_MIO_VREF, and VREF leakage current per pin 15 AILI nput or output leakage current per pin (sample-tested) 15 ACIN(2)PL die input capacitance at the pad 8pFCPIN(2)PS die input capacitance at the pad 8pFIRPUPad pull-up (when selected) @ VIN=0V, VCCO= 330 APad pull-up (when selected) @ VIN=0V, VCCO= 250 APad pull-up (when selected) @ VIN=0V, VCCO= 220 APad pull-up (when selected) @ VIN=0V, VCCO= 150 APad pull-up (when selected) @ VIN=0V, VCCO= 120 AIRPDPad pull-down (when selected) @ VIN= 330 APad pull-down (when selected) @ VIN= 180 AICCADC Analog supply current, analog circuits in powered up state 25mAIBATT(3)Battery supply current 150nARIN_TERM(4)

7 Thevenin equivalent resistance of Programmable input termination to VCCO/2 (UNTUNED_SPLIT_40)284055 Thevenin equivalent resistance of Programmable input termination to VCCO/2 (UNTUNED_SPLIT_50)355065 Thevenin equivalent resistance of Programmable input termination to VCCO/2 (UNTUNED_SPLIT_60)446083 nTemperature diode ideality factor rTemperature diode series resistance 2 values are specified at nominal voltage, 25 measurement represents the die capacitance at the pad, not including the value specified for worst case process at 25 resistance to a VCCO/2 FeedbackZynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)DS187 ( ) July 2, Specification5 Table 4:VIN Maximum Allowed AC Voltage Overshoot and Undershoot for PS I/O and PL HR I/O Banks(1)(2)AC Voltage Overshoot% of UI @ 40 C to 125 CAC Voltage Undershoot% of UI @ 40 C to 125 CVCCO+ + + + + + + + + : total of 200 mA per bank should not be peak voltage of the overshoot or undershoot, and the duration above VCCO+ or below GND , must not exceed the values in this 5.

8 Typical Quiescent Supply CurrentSymbolDescriptionDeviceSpeed GradeUnits-3-2-1-1 LIICCPINTQPS quiescent VCCPINT supply currentXC7Z007SN/A122122N/AmAXC7Z012SN/A 122122N/AmAXC7Z014SN/A122122N/AmAXC7Z010 12212212285mAXC7Z01512212212285mAXC7Z020 12212212285mAXA7Z010N/AN/A122N/AmAXA7Z02 0N/AN/A122N/AmAXQ7Z020N/A12212285mAICCPA UXQPS quiescent VCCPAUX supply currentXC7Z007SN/A1313N/AmAXC7Z012SN/A13 13N/AmAXC7Z014SN/A1313N/AmAXC7Z010131313 11mAXC7Z01513131311mAXC7Z02013131311mAXA 7Z010N/AN/A13N/AmAXA7Z020N/AN/A13N/AmAXQ 7Z020N/A131311mASend FeedbackZynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)DS187 ( ) July 2, Specification6 ICCDDRQPS quiescent VCCO_DDR supply currentXC7Z007SN/A44N/AmAXC7Z012SN/A44N/ AmAXC7Z014SN/A44N/AmAXC7Z0104444mAXC7Z01 54444mAXC7Z0204444mAXA7Z010N/AN/A4N/AmAX A7Z020N/AN/A4N/AmAXQ7Z020N/A444mAICCINTQ PL quiescent VCCINT supply currentXC7Z007SN/A3434N/AmAXC7Z012SN/A77 77N/AmAXC7Z014SN/A7878N/AmAXC7Z010343434 21/23(4)mAXC7Z01577777747/53(4)mAXC7Z020 78787848/54(4)mAXA7Z010N/AN/A34N/AmAXA7Z 020N/AN/A78N/AmAXQ7Z020N/A787848/54(4)mA ICCAUXQPL quiescent VCCAUX supply currentXC7Z007SN/A1818N/AmAXC7Z012SN/A35 35N/AmAXC7Z014SN/A3838N/AmAXC7Z010181818 16mAXC7Z01535353531mAXC7Z02038383834mAXA 7Z010N/AN/A18N/AmAXA7Z020N/AN/A38N/AmAXQ 7Z020N/A383834mAICCOQPL quiescent VCCO supply currentXC7Z007SN/A33N/AmAXC7Z012SN/A33N/ AmAXC7Z014SN/A33N/AmAXC7Z0103333mAXC7Z01 53333mAXC7Z0203333mAXA7Z010N/AN/A3N/AmAX A7Z020N/AN/A3N/AmAXQ7Z020N/A333mATable 5.

9 Typical Quiescent Supply Current (Cont d)SymbolDescriptionDeviceSpeed GradeUnits-3-2-1-1 LISend FeedbackZynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)DS187 ( ) July 2, Specification7 ICCBRAMQPL quiescent VCCBRAM supply currentXC7Z007SN/A33N/AmAXC7Z012SN/A44N/ AmAXC7Z014SN/A66N/AmAXC7Z0103331/2(4)mAX C7Z0154442/2(4)mAXC7Z0206663/4(4)mAXA7Z0 10N/AN/A3N/AmAXA7Z020N/AN/A6N/AmAXQ7Z020 N/A663/4(4) values are specified at nominal voltage, 85 C junction temperatures (Tj) with single-ended SelectIO values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and xilinx Power Estimator (XPE) spreadsheet tool (download at ) estimates operating current. When the required power-on current exceeds the estimated operating current, XPE can display the power-on first value is at , and the second value is at 5:Typical Quiescent Supply Current (Cont d)SymbolDescriptionDeviceSpeed GradeUnits-3-2-1-1 LISend FeedbackZynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)DS187 ( ) July 2, Specification8PS Power-On/Off Power Supply SequencingThe recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on.

10 The PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity. For additional information about PS_POR_B timing requirements refer to recommended power-off sequence is the reverse of the power-on sequence. If VCCPAUX, VCCPLL, and the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) have the same recommended voltage levels, then they can be powered by the same supply and ramped simultaneously. xilinx recommends powering VCCPLL with the same supply as VCCPAUX, with an optional ferrite bead filter. Before VCCPINT reaches at least one of the four following conditions is required during the power-off stage: the PS_POR_B input is asserted to GND, the reference clock to the PS_CLK input is disabled, VCCPAUX is lower than , or VCCO_MIO0 is lower than The condition must be held until VCCPINT reaches to ensure PS eFUSE VCCO_MIO0 and VCCO_MIO1 voltages of : The voltage difference between VCCO_MIO0 /VCCO_MIO1 and VCCPAUX must not exceed for longer than TVCCO2 VCCAUX for each power-on/off cycle to maintain device reliability levels.