Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC …

1 zynq - 7000 SoC. (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics DS191 ( ) July 2, 2018 Product Specification Introduction The zynq - 7000 SoCs are available in -3, -2, -2LI, -1, and All supply voltage and junction temperature specifications -1LQ speed grades, with -3 having the highest performance. are representative of worst-case conditions. The The -2LI devices operate at programmable logic (PL) parameters included are common to popular designs and VCCINT/VCCBRAM = and are screened for lower typical applications. maximum static power. The speed specification of a -2LI. The available device/package combinations are outlined in: device is the same as that of a -2 device. The -1LQ devices operate at the same voltage and speed as the -1Q devices zynq - 7000 SoC Overview (DS190).

2 And are screened for lower power. zynq - 7000 device DC Defense-grade zynq -7000Q SoC Overview (DS196). and AC characteristics are specified in commercial, extended, industrial, and expanded (Q-temp) temperature XA zynq - 7000 SoC Overview (DS188). ranges. Except the operating temperature range or unless This zynq - 7000 SoC data sheet, which covers the otherwise noted, all the DC and AC electrical parameters specifications for the XC7Z030, XA7Z030, XQ7Z030, are the same for a particular speed grade (that is, the timing XC7Z035, XC7Z045, XQ7Z045, XC7Z100, and XQ7Z100. characteristics of a -1 speed grade industrial device are the complements the zynq - 7000 SoC documentation suite same as for a -1 speed grade commercial device). However, available on the Xilinx website at only selected speed grades and/or devices are available in the commercial, extended, or industrial temperature ranges.

3 DC Characteristics Table 1: Absolute Maximum Ratings (1). Symbol Description Min Max Units Processing System (PS). VCCPINT PS internal logic supply voltage V. VCCPAUX PS auxiliary supply voltage V. VCCPLL PS PLL supply V. VCCO_DDR PS DDR I/O supply V. VCCO_MIO(2) PS MIO I/O supply V. VPREF PS input reference voltage V. VPIN(2)(3)(4)(5) PS MIO I/O input voltage VCCO_MIO + V. PS DDR I/O input voltage VCCO_DDR + V. Programmable Logic (PL). VCCINT PL internal supply voltage V. VCCBRAM PL supply voltage for the block RAM memories V. VCCAUX PL auxiliary supply voltage V. PL output drivers supply voltage for HR I/O banks V. VCCO. PL output drivers supply voltage for HP I/O banks V. VCCAUX_IO(4) Auxiliary supply voltage V. Copyright 2012 2018 Xilinx, Inc. Xilinx, the Xilinx logo, zynq , Virtex, Artix, Kintex, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in the United States and other countries.

4 AMBA, AMBA Designer, ARM, Cortex-A9, CoreSight, Cortex, PrimeCell, ARM Powered, and ARM Connected Partner are trademarks of ARM Ltd. All other trademarks are the property of their respective owners. DS191 ( ) July 2, 2018 Send Feedback Product Specification 1. zynq - 7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics Table 1: Absolute Maximum Ratings (1) (Cont'd). Symbol Description Min Max Units VREF Input reference voltage V. I/O input voltage for HR I/O banks VCCO + V. I/O input voltage for HP I/O banks VCCO + V. VIN(3)(4)(5). I/O input voltage (when VCCO = ) for VREF and differential I/O standards V. except TMDS_33(6). VCCBATT Key memory battery backup supply V. GTX Transceiver VMGTAVCC Analog supply voltage for the GTX transmitter and receiver circuits V.

5 VMGTAVTT Analog supply voltage for the GTX transmitter and receiver termination circuits V. VMGTVCCAUX Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX transceivers V. VMGTREFCLK GTX transceiver reference clock absolute input voltage V. Analog supply voltage for the resistor calibration circuit of the GTX transceiver VMGTAVTTRCAL V. column VIN Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage V. IDCIN-FLOAT DC input current for receiver input pins DC coupled RX termination = floating 14 mA. IDCIN-MGTAVTT DC input current for receiver input pins DC coupled RX termination = VMGTAVTT 12 mA. IDCIN-GND DC input current for receiver input pins DC coupled RX termination = GND mA. IDCOUT-FLOAT DC output current for transmitter pins DC coupled RX termination = floating 14 mA.

6 IDCOUT-MGTAVTT DC output current for transmitter pins DC coupled RX termination = VMGTAVTT 12 mA. XADC. VCCADC XADC supply relative to GNDADC V. VREFP XADC reference input relative to GNDADC V. Temperature TSTG Storage temperature (ambient) 65 150 C. Maximum soldering temperature for Pb/Sn component bodies(7) +220 C. TSOL. Maximum soldering temperature for Pb-free component bodies(7) +260 C. Tj Maximum junction temperature(7) +125 C. Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.

7 2. Applies to both MIO supply banks VCCO_MIO0 and VCCO_MIO1. 3. The lower absolute voltage specification always applies. 4. For I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471) or the zynq - 7000 SoC Technical Reference Manual (UG585). 5. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4 and Table 5. 6. See Table 12 for TMDS_33 specifications. 7. For soldering guidelines and thermal considerations, see the zynq - 7000 SoC packaging and pinout Specification (UG865). DS191 ( ) July 2, 2018 Send Feedback Product Specification 2. zynq - 7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics Table 2: Recommended Operating Conditions (1)(2). Symbol Description Min Typ Max Units PS.

8 VCCPINT(3) PS internal logic supply voltage V. VCCPAUX PS auxiliary supply voltage V. VCCPLL PS PLL supply voltage V. VCCO_DDR PS DDR supply voltage V. VCCO_MIO(4) PS supply voltage for MIO banks V. VCCO_DDR + VPIN(5) PS DDR and MIO I/O input voltage V. VCCO_MIO + PL. PL internal supply voltage V. VCCINT(6). PL -2LI ( ) internal supply voltage V. PL block RAM supply voltage V. VCCBRAM(6). PL -2LI ( ) block RAM supply voltage V. VCCAUX PL auxiliary supply voltage V. PL supply voltage for HR I/O banks V. VCCO(7)(8). PL supply voltage for HP I/O banks V. PL auxiliary supply voltage when set to V. VCCAUX_IO(9). PL auxiliary supply voltage when set to V. I/O input voltage VCCO + V. VIN(5) I/O input voltage (when VCCO = ) for VREF and differential V. I/O standards except TMDS_33(10).

9 Maximum current through any (PS or PL) pin in a powered or IIN(11) 10 mA. unpowered bank when forward biasing the clamp diode VCCBATT(12) Battery voltage V. GTX Transceiver Analog supply voltage for the GTX transceiver QPLL frequency V. range GHz(14)(15). VMGTAVCC(13). Analog supply voltage for the GTX transceiver QPLL frequency range > GHz Analog supply voltage for the GTX transmitter and receiver VMGTAVTT(13) V. termination circuits VMGTVCCAUX(13) Auxiliary analog QPLL voltage supply for the transceivers V. Analog supply voltage for the resistor calibration circuit of the VMGTAVTTRCAL(13) V. GTX transceiver column XADC. VCCADC XADC supply relative to GNDADC V. VREFP Externally supplied reference voltage V. DS191 ( ) July 2, 2018 Send Feedback Product Specification 3.

10 zynq - 7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics Table 2: Recommended Operating Conditions (1)(2) (Cont'd). Symbol Description Min Typ Max Units Temperature Junction temperature operating range for commercial (C). 0 85 C. temperature devices Junction temperature operating range for extended (E). 0 100 C. temperature devices Tj Junction temperature operating range for industrial (I). 40 100 C. temperature devices Junction temperature operating range for expanded (Q). 40 125 C. temperature devices Notes: 1. All voltages are relative to ground. The PL and PS share a common ground. 2. For the design of the power distribution system consult the zynq - 7000 SoC PCB Design Guide (UG933). 3. When the processor cores operate FCPU_6X4X_621_MAX at 1 GHz (-3E speed grade) or when the DDR interface operates at 1333 Mb/s, the VCCPINT minimum is and the VCCPINT maximum is 4.