SystemVerilog Implicit Port Connections - Simulation ...

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DesignCon 20051SystemVerilog Implicit Port ConnectionsRev - Last Update - 04/01/2005- Simulation & SynthesisExpert Verilog, SystemVerilog & Synthesis TrainingSystemVerilog Implicit Port Connections - Simulation & SynthesisClifford E. Cummings, Sunburst Design, Accellera SystemVerilog language[3] includes two new features designed to remove muchof the tedium and verbosity related to building top-level ASIC and FPGA designs frominstantiated sub-blocks. These enhancements permit one of two forms of Implicit portconnectionsNOTE: An updated copy of this paper can be found at 20052SystemVerilog Implicit Port ConnectionsRev - Last Update - 04/01/2005- Simulation & Synthesis1.

connections. Unfortunately the use of named port connections in a top-level ASIC or FPGA design is typically a very verbose and redundant set of connections that requires multiple pages of coding to describe. Often, most of the top-level module port names match the equivalent net or bus connections.

  Connection, Ports, Systemverilog, Implicit, Systemverilog implicit port connections