Appendix A. Verilog Code of Design Examples

Appendix A. Verilog code of Design ExamplesThe next pages contain the Verilog 1364 -2001 code of all Design old style Verilog 1364 -1995 code can be found in [441]. The synthesisresults for the Examples are listed on page **// ieee STD 1364 -2001 Verilog file: Author-EMAIL: example //----> Interface#(parameter WIDTH =8) // Bit width(input clk, // System clockinput reset, // Asynchronous resetinput [WIDTH-1:0] a, b, op1, // Vector type inputsoutput [WIDTH-1:0] sum, // Vector type inputsoutput [WIDTH-1:0] c, // Integer outputoutput reg [WIDTH-1:0] d); // Integer output// ---------------------------------------- ----------------reg [WIDTH-1:0] s; // Infer FF with alwayswire [WIDTH-1:0] op2, op3;wire [WIDTH-1:0] a_in, b_in;assign op2 = b; // Only one vector type in Verilog ;// no conversion int -> logic vector necessarylib_add_sub add1 //----> Component instantiation(.)

The next pages contain the Verilog 1364-2001 code of all design examples. The old style Verilog 1364-1995 code can be found in [441]. The synthesis results for the examples are listed on page 881. //***** // IEEE STD 1364-2001 Verilog file: example.v // Author-EMAIL: Uwe.Meyer-Baese@ieee.org //*****

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