Appendix I Synthesizable and Non-Synthesizable Verilog ...

Appendix I. Synthesizable and Non-Synthesizable Verilog Constructs The list of Synthesizable and Non-Synthesizable Verilog constructs is tabu-lated in the following Table Verilog Used for Synthesizable Non-Synthesizable Constructs construct Construct module The code inside the module and Yes No the endmodule consists of the declarations and functionality of the design Instantiation If the module is Synthesizable Yes No then the instantiation is also Synthesizable initial Used in the test benches No Yes always Procedural block with the reg Yes No type assignment on LHS side. The block is sensitive to the events assign Continuous assignment with Yes No wire data type for modeling the combinational logic primitives UDP's are Non-Synthesizable Yes No whereas other Verilog primitives are Synthesizable force and These are used in test benches No Yes release and Non-Synthesizable delays Used in the test benches and No Yes synthesis tool ignores the delays fork and join Used during si

Code converters, 49 Coding guidelines, 79 Combinational logic, 10, 27 Combinational loop, 245 Combinational path, 286 Combinational path group, 284 Combinational shifters, 192 Comparators, 46 Compile, 267 Compile-characterize, 302 Compiler, 314 Computational blocks, 386 Concentration and replication, 18 Concurrent, 10 Concurrent execution, 161

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