Transcription of DDR4 Simulation Guidelines - Intel
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DDR4 Simulation Guidelines - Intel
ddr4 Simulation Guidelines Introduction These Guidelines were created for use with the existing Memory Design Guidelines and provide information on the simulations necessary to create the information needed for those Guidelines that are very important to. This set of Guidelines will be created using Arria 10 ibis models. Background Knowledge Source The Altera External Memory Interface Handbook provides a thorough explanation of ddr4 topologies and board design Guidelines for ddr4 systems. The External Memory Interface (EMIF) Handbook is very useful in understanding what needs to be done to create a successful system. The EMIF handbook Guidelines were created using useful numbers for spacing of the traces and other constraints for the system. If a 2D simulator available figures can be created for signal parallelism rules and length matching.
A. Format of the output file, one can select HSPICE or IBIS, for our us it is IBIS B. IBIS Version: using 5.0 allows per pin RLC package model generation with mutual coupling C. Enabling model selector creates an IBIS files with multiple models for what-if simulation D. Per pin RLC package models deliver accurate package data
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