Transcription of Latches, the D Flip-Flop & Counter Design - UC Santa Barbara
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Latches, the D Flip-Flop & Counter DesignECE 152A Winter 2012 February 6, 2012 ECE 152A -Digital Design Principles2 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor Basic Latch Gated SR Latch Gated SR Latch with NAND Gates Gated D Latch Effects of Propagation DelaysFebruary 6, 2012 ECE 152A -Digital Design Principles3 Reading Assignment Brown and Vranesic(cont) 7 Flip-Flops, Registers, Counters and a Simple Processor (cont) Master-Slave and Edge-Triggered D Flip-Flops Master-Slave D Flip-Flop Edge-Triggered D Flip-Flop D Flip-Flop with Clear and Preset Flip-Flop Timing Parameters (2ndedition)February 6, 2012 ECE 152A -Digital Design Principles4 Reading Assignment Roth 11 Latches and Flip-Flops Introduction Set-Reset Latch Gated D Latch Edge-Triggered D Flip-FlopFebruary 6, 2012 ECE 152A -Digital Design Principles5 Reading Assignment Roth(cont) 12 Registers and Counters Registers and Register Transf
7.4.3 D Flip-Flop with Clear and Preset ... Ring Oscillator ... February 6, 2012 ECE 152A - Digital Design Principles 18 The SR Latch (cont)
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