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PCI Express Basics & Background

Copyright 2014, PCI-SIG, All Rights Reserved1 PCI Express Basics & BackgroundRichard SolomonSynopsysPCIeTechnology Seminar2 AcknowledgementsThanks are due to Ravi Budruk, Mindshare, Inc. for much of the material on PCI Express Basics2 Copyright 2014, PCI-SIG, All Rights ReservedPCIeTechnology SeminarAgenda PCI Express Background PCI Express Basics PCI Express Recent DevelopmentsCopyright 2014, PCI-SIG, All Rights Reserved3 PCIeTechnology Seminar4 PCI Express BackgroundCopyright 2014, PCI-SIG, All Rights ReservedPCIeTechnology SeminarCopyright 2014, PCI-SIG, All Rights Reserved5 Revolutionary AND Evolutionary PCI (1992/1993) Revolutionary Plug and Play jumperlessconfiguration (BARs) Unprecedented bandwidth 32-bit / 33 MHz 133MB/sec 64-bit / 66 MHz 533MB/sec Designed from day 1 for bus-mastering adapters Evolutionary System BIOS maps devices then operating systems boot and run without further knowledge of PCI PCI-aware O/S could gain improved functionality PCI (1995) doubled bandwidth with 66 MHz modePCIeTechnology SeminarCopyright 2014, PCI-SIG, All Rights Reserved6 Revolutionary AND Evolutionary PCI-X (1999)

PCI Express Features Dual Simplex point-to-point serial connection Independent transmit and receive sides Scalable Link Widths x1, x2, x4, x8, x12, x16, x32 Scalable Link Speeds 2.5, 5.0 and 8.0GT/s (16GT/s coming in 4.0) Packet based transaction protocol PCIe Device A PCIe Device B Link (x1, x2, x4, x8, x12, x16 or x32) Packet Packet

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