Transcription of Phase Locked Loop Circuits
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Phase Locked Loop Circuits
Phase Locked Loop Circuits Reading: General PLL Description: T. H. Lee, Chap. 15. Gray and Meyer, Clock generation: B. Razavi, Design of Analog CMOS Integrated Circuits , Chap. 15, McGraw-Hill, 2001. 1. Definition. A PLL is a feedback system that includes a VCO, Phase detector, and low pass filter within its loop. Its purpose is to force the VCO to replicate and track the frequency and Phase at the input when in lock. The PLL is a control system allowing one oscillator to track with another. It is possible to have a Phase offset between input and output, but when Locked , the frequencies must exactly track.
minimize the required phase offset or error, the PLL loop gain, KD KO, should be maximized, since KD KDKO V1 1 0 0 ω ω φ − = = Thus, a high loop gain is beneficial for reducing phase errors. 4. PLL dynamic response: To see how the PLL works, suppose that we introduce a phase step at the input at t = t1. φin =ω1t +φ0 +φ1u(t −t1)
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