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SystemVerilog Implicit Port Connections - Simulation ...

DesignCon 20051 SystemVerilog Implicit Port ConnectionsRev - Last Update - 04/01/2005- Simulation & SynthesisExpert Verilog, SystemVerilog & Synthesis TrainingSystemVerilog Implicit Port Connections - Simulation & SynthesisClifford E. Cummings, Sunburst Design, Accellera SystemVerilog language[3] includes two new features designed to remove muchof the tedium and verbosity related to building top-level ASIC and FPGA designs frominstantiated sub-blocks. These enhancements permit one of two forms of Implicit portconnectionsNOTE: An updated copy of this paper can be found at 20052 SystemVerilog Implicit Port ConnectionsRev - Last Update - 04/01/2005- Simulation & Synthesis1. Implicit port connectionsVerilog[2] and VHDL both have the ability to instiantiate modules using either positional ornamed port Connections . Positional ports are subject to mis-ordered incorrect Connections , whichis why most experienced companies have internal guidelines requiring the use of named portconnections.

Example 2 - CALU model built using named port connections 2.3 The .name implicit port connection enhancement SystemVerilog introduces the ability to do .name implicit port connections. Whenever the port name and size matches the connecting net or bus name and size, the port name can be listed just once with a leading period as shown in Example 3.

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