Verilog-A Language Reference Manual

verilog -ALanguage Reference ManualAnalog Extensions to verilog HDLV ersion 1, 1996 Open verilog InternationalNo part of this work covered by the copyright hereon may be reproduced or used in any form or by any means --- graphic, electronic, or mechanical, including photocopying, recording, taping, or information storage andretrieval systems --- without the prior written approval of Open verilog copies of this Manual may be purchased by contacting Open verilog international at the addressshown information contained in this draft Manual represents the definition of the Verilog-A hardware descriptionlanguage as proposed by OVI (Analog TSC) as of January, 1996. Open verilog international makes no warran-ties whatsoever with respect to the completeness, accuracy, or applicability of the information in this draft man-ual to a user s requirements. This Language is not yet fully defined and is subject to change. It is suitable forlearning how to do analog modeling and as a vehicle for providing feedback to the standards committee.

Verilog-A Language Reference Manual Analog Extensions to Verilog HDL Version 1.0 August 1, 1996 Open Verilog International

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