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World Class Verilog & SystemVerilog TrainingSystemVerilog Event Regions,Race Avoidance & GuidelinesClifford E. CummingsArturo SalzSunburst Design, IEEE1800 SystemVerilog Standard includes new event regions primarily added to reducerace conditions between verification code and SystemVerilog designs. The new regions alsofacilitate race-free Assertion Based Verification (ABV).This paper details common Verilog verification strategies and how the new event regionsfacilitate construction of race-free testbenches using new SystemVerilog capabilities. An in-depth explanation of SystemVerilog event regions is included to help understand how race-reduction goals have been met.

SNUG Boston 2006 5 SystemVerilog Event Regions Rev 1.2 Race Avoidance & Guidelines 2 Event Regions - Verilog-2001 -vs- SystemVerilog First we need to introduce a couple of definitions, simulation time and time slot. "The term simulation time is used to refer to the time value maintained by the simulator to model the actual time it would take for the system description being simulated.

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