Arithmetic / Logic Unit – ALU Design
• 32-bit adder is built out of 32 1-bit adders Input Output Figure B.5.2 Figure B.5.5 1-bit Adder 1-bit Adder Truth Table From the truth table and after minimization, we can have this design for CarryOut Figure B.5.3 . 4 g. babic Presentation F 7 32-bit Adder + + + + a0 b0 a2 b2 a1 b1 a31 b31 sum0 sum31 sum2 sum1 Cout Cin Cout Cout Cout ...
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