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AXI IIC Bus Interface v2 - Xilinx
Design Files VHDL Example Design VHDL Test Bench VHDL Constraints File XDC delivered with IP generation. Simulation Model None Supported S/W Driver(2) Standalone and Linux Tested Design Tools(3) Design Entry Tools Vivado® Design Suite Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide. Synthesis Tools Vivado ...
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