Intel SGX Explained
enclave code does not directly service an interrupt, fault (e.g., a page fault) or VM exit. Instead, the CPU first per-forms an Asynchronous Enclave Exit (x5.4.3) to switch from enclave code to ring 3 code, and then services the interrupt, fault, or VM exit. The CPU performs an AEX by saving the CPU state into a predefined area inside the
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