Selecting the Optimum PCIe Clock Source
Description Symbol Limit Units Common Clock Architecture Gen 1 Random Jitter Rj 4.7 ps pk-pk Deterministic Jitter Dj 41.9 ps RMS Gen 2 High Frequency RMS Jitter Measured from 10 kHz to 50MHz J RMS-HF 3.1 ps RMS Gen 3 High Frequency RMS Jitter Measured from 10 kHz to 50MHz J RMS-HF 1 ps RMS
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