Vivado tutorial - Xilinx
1-1-4. Enter tutorial in the Project name field. Make sure that the Create Project Subdirectory box is checked. Click Next. Figure 3. Project Name and Location entry 1-1-5. Select RTL Project option in the Project Type form, and click Next. 1-1-6. Select Verilog as the Target language and Simulator language in the Add Sources form. 1-1-7.
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