SN54/74HCT CMOS LOGIC FAMILY APPLICATIONS …

1 1SN54/74 HCTCMOS LOGIC FamilyApplications and RestrictionsSCLA011 May 1996 2 IMPORTANT NOTICET exas Instruments (TI) reserves the right to make changes to its products or to discontinue anysemiconductor product or service without notice, and advises its customers to obtain the latestversion of relevant information to verify, before placing orders, that the information being reliedon is warrants performance of its semiconductor products and related software to the specificationsapplicable at the time of sale in accordance with TI s standard warranty.

2 Testing and other qualitycontrol techniques are utilized to the extent TI deems necessary to support this testing of all parameters of each device is not necessarily performed, except thosemandated by government APPLICATIONS using semiconductor products may involve potential risks of death,personal injury, or severe property or environmental damage ( Critical APPLICATIONS ).TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, ORWARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS , DEVICESOR SYSTEMS OR OTHER CRITICAL of TI products in such APPLICATIONS is understood to be fully at the risk of the of TI products in such APPLICATIONS requires the written approval of an appropriate TI concerning potential risk APPLICATIONS should be directed to TI through a local SCsales order to minimize risks associated with the customer s APPLICATIONS .

3 Adequate design andoperating safeguards should be provided by the customer to minimize inherent or assumes no liability for APPLICATIONS assistance, customer product design, softwareperformance, or infringement of patents or services described herein. Nor does TI warrant orrepresent that any license, either express or implied, is granted under any patent right, copyright,mask work right, or other intellectual property right of TI covering or relating to any combination,machine, or process in which such semiconductor products or services might be or are 1996, Texas Instruments IncorporatediiiContentsTitlePageIntroduc tion1.

4 TTL/HC Interface1.. Operating Voltages of HCT Circuits2.. Noise of HCT Circuits3.. Power Consumption of HCT Circuits6.. Delay Times9.. Bergeron Analysis9.. Summary11.. List of IllustrationsFigureTitlePage1 TTL- cmos Interface With Open-Collector Output and Pullup Resistor1.. 2 Noise Margin3.. 3 Specified Noise Margins for HC, HCT, and TTL Devices3.. 4 Crosstalk (First Case)5.. 5 Crosstalk (Second Case)5.. 6 Input-Stage Structure of HC and HCT Circuits7.. 7 Supply Current as a Function of the Input Voltage8.. 8 Current Consumption as a Function of Frequency8.

5 9 Bergeron Diagram, SN74 ALS245 Driver9.. 10 Line Reflections, SN74 ALS245 Driver10.. 11 Bergeron Diagram, SN74HC245 Driver10.. 12 Line Reflections, SN74HC245 Driver11.. iv1 IntroductionThis report describes APPLICATIONS , features, and system design of the SN54/74 HCT high-speed cmos FAMILY . To simplifyinterfacing of TTL outputs to high-speed cmos inputs, Texas Instruments (TI) introduced HCT circuits, a subgroup of its HCfamily. HCT features and functions are identical to HC devices with the exception of modified input circuitry, which makesthe input threshold voltage compatible with TTL circuits.

6 HCT outputs are similar to the HC InterfaceTTL output voltages and HC input voltages are incompatible, especially between the TTL high-level output voltage (VOH)and the HC high-level input voltage (VIH). This problem can be solved in three different ways. The first way is to use HCTdevices with their TTL-compatible input voltages to interface between TTL and HC circuits. Another solution is to providepullup resistors at the TTL outputs to ensure an adequate high-level TTL output voltage. The third method requires the useof level the three alternatives mentioned, using HCT circuits to solve the incompatibility problem, is the most convenient.

7 Designedto meet the requirements of this application, HCT devices allow the engineer to benefit from the advantages of HC devices(low power consumption) without using discrete components, such as pullup resistors.+5 VRpFigure 1. TTL- cmos Interface With Open-Collector Output and Pullup ResistorUsing pullup resistors to accommodate TTL output signals to interface with HC input circuits (see Figure 1), the designengineer has to choose the resistance that is appropriate for the application. The minimum value of the resistor is determinedby the maximum current IOL that a TTL circuit can supply at the low-level output (VOL).

8 Rpmin+VCCmax*VOLminIOL)n IILwhere n is the number of HC inputs to be driven, and IIL is their input current. IIL, having a value of only a few nanoamperes,is negligible in all the case of a SN74 ALS03, the following equation defines Rpmin:Rpmin+ V* V8mA+640 WTo calculate the upper limit of this resistor, a sufficient VIH high level must be +VCC*VIHminn IIHIn this situation, the input current of HC devices is negligible and very high values also are obtained.(1)(2)(3) 2 When calculating the maximum allowable resistance, it is important to ensure that the maximum allowable rise time(tr = 500 ns) at the HC input is not exceeded.

9 The following equation then applies:VIH+VCC 1*e*tRp C where C is the total load capacitance in the circuit. C is composed of the output capacitance of the driving gate ( 10 pF), thetotal input capacitances of gates to be driven ( 5 pF each), and the line capacitance ( 1 pF/cm). The actual value is calculatedby solving the equation for Rp:Rp+*tC ln 1* V5V Assuming the total capacitance, C, is 30 pF, the maximum resistor is:Rp+*500 ns30 pF ln 1* V5V +14 kWFaster rise times result in lower impedance and more power consumption.

10 The previous calculation is based on the assumptionthat the driving gate has an open collector. Conditions become more satisfactory, however, when a gate with totem-pole output( , SN74 ALS00) is used. In that case, the gate output provides the voltage to be brought up to the value VOH = V in lessthan 10 ns (the rise time of the TTL signal). The pullup resistor only has to pull the level to V within the desired to the previous formula, and with a required rise time of tr = 50 ns, the resistor is defined by the following calculation:Rpmax+*50 ns*10 ns30 pF ln 1* V* V5V* V + kWThe upper limiting value of the resistor is primarily dictated by the rise time required.