MSP430x2xx Family User's Guide (Rev. J) - TI.com

1 MSP430x2xx Family User's Guide Literature Number: SLAU144J. December 2004 Revised July 2013. Contents 21. 1 Introduction .. 23. Architecture .. 24. Flexible Clock System .. 24. Embedded Emulation .. 25. Address Space .. 25. Flash/ROM .. 25. RAM .. 26. Peripheral Modules .. 26. Special Function Registers (SFRs) .. 26. Memory Organization .. 26. MSP430x2xx Family Enhancements .. 27. 2 System Resets, Interrupts, and Operating Modes .. 28. System Reset and Initialization .. 29. Brownout Reset (BOR) .. 29. Device Initial Conditions After System Reset .. 30. Interrupts .. 31. (Non)-Maskable Interrupts (NMI) .. 31. Maskable Interrupts .. 34. Interrupt Processing .. 35. Interrupt Vectors.

2 37. Operating Modes .. 38. Entering and Exiting Low-Power Modes .. 40. Principles for Low-Power Applications .. 40. Connection of Unused Pins .. 41. 3 CPU .. 42. CPU Introduction .. 43. CPU Registers .. 44. Program Counter (PC) .. 44. Stack Pointer (SP) .. 45. Status Register (SR) .. 45. Constant Generator Registers CG1 and CG2 .. 46. General-Purpose Registers R4 to R15 .. 47. Addressing Modes .. 47. Register Mode .. 49. Indexed Mode .. 50. Symbolic Mode .. 51. Absolute Mode .. 52. Indirect Register Mode .. 53. Indirect Autoincrement Mode .. 54. Immediate Mode .. 55. Instruction Set .. 56. Double-Operand (Format I) Instructions .. 57. Single-Operand (Format II) Instructions.

3 58. Jumps .. 59. 2 Contents SLAU144J December 2004 Revised July 2013. Submit Documentation Feedback Copyright 2004 2013, Texas Instruments Incorporated Instruction Cycles and Lengths .. 60. Instruction Set Description .. 62. Instruction Set Details .. 64. 4 CPUX .. 115. CPU Introduction .. 116. Interrupts .. 118. CPU Registers .. 119. Program Counter (PC) .. 119. Stack Pointer (SP) .. 119. Status Register (SR) .. 121. Constant Generator Registers (CG1 and CG2) .. 122. General-Purpose Registers (R4 to R15) .. 123. Addressing Modes .. 125. Register Mode .. 126. Indexed Mode .. 127. Symbolic Mode .. 131. Absolute Mode .. 136. Indirect Register Mode .. 138. Indirect Autoincrement Mode.

4 139. Immediate Mode .. 140. MSP430 and MSP430X Instructions .. 142. MSP430 Instructions .. 142. MSP430X Extended Instructions .. 147. Instruction Set Description .. 160. Extended Instruction Binary Descriptions .. 161. MSP430 Instructions .. 163. MSP430X Extended Instructions .. 215. MSP430X Address Instructions .. 257. 5 Basic Clock Module+ .. 272. Basic Clock Module+ Introduction .. 273. Basic Clock Module+ Operation .. 275. Basic Clock Module+ Features for Low-Power Applications .. 276. Internal Very-Low-Power Low-Frequency Oscillator (VLO) .. 276. LFXT1 Oscillator .. 276. XT2 Oscillator .. 277. Digitally-Controlled Oscillator (DCO) .. 277. DCO Modulator .. 279. Basic Clock Module+ Fail-Safe Operation.

5 279. Synchronization of Clock Signals .. 280. Basic Clock Module+ Registers .. 282. DCOCTL, DCO Control Register .. 283. BCSCTL1, Basic Clock System Control Register 1 .. 283. BCSCTL2, Basic Clock System Control Register 2 .. 284. BCSCTL3, Basic Clock System Control Register 3 .. 285. IE1, Interrupt Enable Register 1 .. 286. IFG1, Interrupt Flag Register 1 .. 286. 6 DMA Controller .. 287. DMA Introduction .. 288. DMA Operation .. 290. DMA Addressing Modes .. 290. DMA Transfer Modes .. 291. Initiating DMA Transfers .. 297. SLAU144J December 2004 Revised July 2013 Contents 3. Submit Documentation Feedback Copyright 2004 2013, Texas Instruments Incorporated Stopping DMA Transfers.

6 298. DMA Channel Priorities .. 299. DMA Transfer Cycle Time .. 299. Using DMA With System Interrupts .. 299. DMA Controller Interrupts .. 300. Using the USCI_B I2C Module with the DMA Controller .. 300. Using ADC12 with the DMA Controller .. 301. Using DAC12 With the DMA Controller .. 301. Writing to Flash With the DMA Controller .. 301. DMA Registers .. 302. DMACTL0, DMA Control Register 0 .. 303. DMACTL1, DMA Control Register 1 .. 303. DMAxCTL, DMA Channel x Control Register .. 304. DMAxSA, DMA Source Address Register .. 305. DMAxDA, DMA Destination Address Register .. 306. DMAxSZ, DMA Size Address Register .. 306. DMAIV, DMA Interrupt Vector Register .. 307. 7 Flash Memory Controller.

7 308. Flash Memory Introduction .. 309. Flash Memory Segmentation .. 309. SegmentA .. 310. Flash Memory Operation .. 311. Flash Memory Timing Generator .. 311. Erasing Flash Memory .. 312. Writing Flash Memory .. 315. Flash Memory Access During Write or Erase .. 320. Stopping a Write or Erase Cycle .. 321. Marginal Read Mode .. 321. Configuring and Accessing the Flash Memory Controller .. 321. Flash Memory Controller Interrupts .. 321. Programming Flash Memory Devices .. 321. Flash Memory Registers .. 323. FCTL1, Flash Memory Control Register .. 324. FCTL2, Flash Memory Control Register .. 324. FCTL3, Flash Memory Control Register .. 325. FCTL4, Flash Memory Control Register.

8 326. IE1, Interrupt Enable Register 1 .. 326. 8 Digital I/O .. 327. Digital I/O Introduction .. 328. Digital I/O Operation .. 328. Input Register PxIN .. 328. Output Registers PxOUT .. 328. Direction Registers PxDIR .. 329. Pullup/Pulldown Resistor Enable Registers PxREN .. 329. Function Select Registers PxSEL and PxSEL2 .. 329. Pin Oscillator .. 330. P1 and P2 Interrupts .. 331. Configuring Unused Port Pins .. 332. Digital I/O Registers .. 333. 9 Supply Voltage Supervisor (SVS) .. 335. Supply Voltage Supervisor (SVS) Introduction .. 336. SVS Operation .. 337. Configuring the SVS .. 337. 4 Contents SLAU144J December 2004 Revised July 2013. Submit Documentation Feedback Copyright 2004 2013, Texas Instruments Incorporated SVS Comparator Operation.

9 337. Changing the VLDx Bits .. 337. SVS Operating Range .. 338. SVS Registers .. 339. SVSCTL, SVS Control Register .. 340. 10 Watchdog Timer+ (WDT+) .. 341. Watchdog Timer+ (WDT+) Introduction .. 342. Watchdog Timer+ Operation .. 344. Watchdog Timer+ Counter .. 344. Watchdog Mode .. 344. Interval Timer Mode .. 344. Watchdog Timer+ Interrupts .. 344. Watchdog Timer+ Clock Fail-Safe Operation .. 345. Operation in Low-Power Modes .. 345. Software Examples .. 345. Watchdog Timer+ Registers .. 346. WDTCTL, Watchdog Timer+ Register .. 347. IE1, Interrupt Enable Register 1 .. 348. IFG1, Interrupt Flag Register 1 .. 348. 11 Hardware Multiplier .. 349. Hardware Multiplier Introduction.

10 350. Hardware Multiplier Operation .. 350. Operand Registers .. 351. Result Registers .. 351. Software Examples .. 352. Indirect Addressing of RESLO .. 353. Using Interrupts .. 353. Hardware Multiplier Registers .. 354. 12 Timer_A .. 355. Timer_A Introduction .. 356. Timer_A Operation .. 357. 16-Bit Timer Counter .. 357. Starting the Timer .. 358. Timer Mode Control .. 358. Capture/Compare Blocks .. 362. Output Unit .. 363. Timer_A Interrupts .. 367. Timer_A Registers .. 369. TACTL, Timer_A Control Register .. 370. TAR, Timer_A Register .. 371. TACCRx, Timer_A Capture/Compare Register x .. 371. TACCTLx, Capture/Compare Control Register .. 372. TAIV, Timer_A Interrupt Vector Register.