Transcription of MOSFET SPICE Model SPICE models the drain …
1 Lecture #25 (10/24/01) MOSFET SPICE ModelqSPICE models the drain current (IDS) of an n-channelMOSFET using:Cut-off: ()IDS = 0 Linear: ()Saturation: ()VGSVTH 0 VDSVGSVTH IDSKP2--------WLeff----------- VDS2 VGSVTH ()VDSVDS []1 LAMBDA VDS +()=0 VGSVTH VDS IDSKP2--------WLeff----------- VGSVTH ()21 LAMBDA VDS +()=Lecture #25 (10/24/01) MOSFET SPICE ModelqThreshold voltage is given by:qSPICE definition for channel length (Leff):Leff= L - 2 LDwhere: L = length of the polysilicon gateLD = gate overlap of the source and drainVTHVTOGAMMA2 PHI VBS 2 PHI ()+=Lecture #25 (10/24/01) MOSFET SPICE Modelqn-channel MOSFET is defined by the SPICE statement:Mname D G S B MODnameL=_W=_AD=_AS=_PD=_PS=_NRD=_NRS=_w here: name = name of the device (up to 7 characters)D, G, S, B = drain , gate, source, and substrate node numbersMODname = Model name for the device (see below)L = polysilicon gate length (see figure)W = polysilicon gate width (see figure)AD = drain area (see figure)AS = source area (see figure)PD = perimeter of drain diffusion (not including edge under gate)PS = perimeter of source diffusion (not including edge under gate)Lecture #25 (10/24/01) MOSFET SPICE ModelNRD = number of squares in drain diffusionNRS = number of squares in source diffusionLecture #25 (10/24/01) MOSFET SPICE ModelqMOSFET Model statement is.
2 MODELMOD namexMOSVTO=_KP=_GAMMA=_PHI=_LAMBDA=_RD= _RS=_RSH=_CBD=_CBS=_CJ=_MJ=_CJSW=_MJSW=_ PB=_IS=_CGDO=_CGSO=_CGBO=_TOX=_LD=_where : x = N (for NMOS) or P (for PMOS)CGDO, CGSO, CGBO = gate overlap capacitance with drain , source, bodyRD = drain contact resistance ( )RS = source contact resistance ( )RSH = sheet resistance of drain /source diffusions( /square; NRD and NRS must be specified)IS = diode saturation current for pn junctions at the drain and sourceLecture #25 (10/24/01) MOSFET SPICE ModelqMOSFET Model statement (cont.):CBD = zero-bias drain -substrate capacitance (F)CBS = zero-bias source-substrate capacitance (F)PB = built-in potential for the substrate junctions (V)MJ = bulk junction grading coefficientCBDVBD()CBD1 VBDPB ()MJ------------------------------------ -----------=CBSVBS()CBS1 VBSPB ()MJ------------------------------------ ----------=Lecture #25 (10/24/01) MOSFET SPICE ModelqMore accurate simulations incorporate both the planarjunctioncapacitanceandperimeter(si dewall)capacitances as:where.
3 CJ = zero-bias planar substrate junction capacitance (F/m2)CJSW = zero-bias planar sidewall junction capacitance (F/m)MJSW = sidewall junction grading coefficientCBDVBD()CJ AD 1 VBDPB ()MJ------------------------------------ -----------CJSW PD 1 VBDPB ()MJSW---------------------------------- ----------------------+=CBSVBS()CJ AS 1 VBSPB ()MJ------------------------------------ ----------CJSW PS 1 VBSPB ()MJSW---------------------------------- ---------------------+=Lecture #25 (10/24/01) MOSFET SPICE ModelqThese and remaining nMOS Model parameters:ParameterSymbolSPICE nameUnitsStandardValueChannel lengthLLEFFmPolysilicon gate lengthLgateLmGate-source overlapLDLDm0 Transconductance parameter nCox KPA/V250 x 10-6 Threshold length modulationparameter (L in m)Backgate effect parameter GAMMAV1 potential #25 (10/24/01)Gate oxide thicknesstoxTOXang-stroms150 Gate- drain overlap capacitanceCgdCGDOF/m5 x 10-10 Gate-source overlap capacitanceCgsCGSOF/m5 x 10-10 Zero-bias planar substratedepletion capacitanceCj0 CJF/m210-4 Zero-bias sidewall substratedepletion capacitanceCJSWF/m5 x 10-10 Substrate junction potential substrate junction substrate junction grad-ing
