MARIE: An Introduction to a Simple Computer

1 1CS 3401 Comp. Org. & Assembly Marie -- Chapter 41 MARIE: An Introduction to a MARIE: An Introduction to a Simple ComputerSimple ComputerCS 3401 Comp. Org. & Assembly Marie -- Chapter 42 OutlineOutlineLearn the components common to every modern Computer able to explain how each component contributes to program a Simple architecture invented to illuminate these basic concepts, and how it relates to some real how the program assembly process 3401 Comp. Org. & Assembly Marie -- Chapter IntroductionChapter 1 presented a general overview of Computer Chapter 2, we discussed how data is stored and manipulated by various Computer system 3 described the fundamental components of digital this background, we can now understand how Computer components work, and how they fit together to create useful Computer 3401 Comp.

2 Org. & Assembly Marie -- Chapter CPU Basic and CPU Basic and OrganizationThe Computer s CPU fetches, decodes, and executes program two principal parts of the CPU are the datapathand the control datapathconsists of an arithmetic-logic unit and storage units (registers) that are interconnected by a data bus that is also connected to main memory. Various CPU components perform sequenced operations according to signals provided by its control 3401 Comp. Org. & Assembly Marie -- Chapter CPU Basic and CPU Basic and OrganizationRegistershold data -- addresses, program counters, data -- that can be readily accessed by the of a register varies according to the number of registers varies from architecture to can be implemented using D 32-bit register requires 32 D arithmetic-logic unit (ALU) carries out logical and arithmetic operations as directed by the control control unit determines which actions to carry out according to the values in a program counterregister and a status 3401 Comp.

3 Org. & Assembly Marie -- Chapter The The BUSThe CPU shares data with other system components by way of a data busis a set of wires that simultaneously convey a single bit along each types of buses are commonly found in Computer systems: point-to-point, and is a point-to-point bus configuration:CS 3401 Comp. Org. & Assembly Marie -- Chapter The The BUSB uses consist of data lines, control lines, and address the data lines convey bits from one device to another, control lines determine the direction of data flow, and when each device can access the lines determine the location of the source or destination of the 3401 Comp. Org. & Assembly Marie -- Chapter The The BUS3CS 3401 Comp. Org. & Assembly Marie -- Chapter The The BUSA multipointbus is shown a multipoint bus is a shared resource, access to it is controlled through protocols, which are built into the hardware.

4 CS 3401 Comp. Org. & Assembly Marie -- Chapter 410In a master-slave configuration, where more than one device can be the bus master, concurrent bus master requests must be categories of bus arbitration are:Daisy chain:Permissions are passed from the highest-priority device to the parallel:Each device is directly connected to an arbitration using self-detection:Devices decide which gets the bus among using collision-detection:Any device can try to use the bus. If its data collides with the data of another device, it tries The The BUSCS 3401 Comp. Org. & Assembly Marie -- Chapter ClocksEvery Computer contains at least one clock that synchronizes the activities of its fixed number of clock cycles are required to carry out each data movement or computational clock frequency, measured in megahertz or gigahertz, determines the speed with which all operations are carried cycle time is the reciprocal of clock 800 MHz clock has a cycle time of 3401 Comp.

5 Org. & Assembly Marie -- Chapter ClocksClock speed should not be confused with CPU CPU time required to run a program is given by the general performance equation:We see that we can improve CPU throughput when we reduce the number of instructions in a program, reduce the number of cycles per instruction, or reduce the number of nanoseconds per clock operation Intel 286 required 20 clock cyclesPentium required 1 clock cycle4CS 3401 Comp. Org. & Assembly Marie -- Chapter Input/Output Input/Output SubsystemA Computer communicates with the outside world through its input/output (I/O) devices connect to the CPU through various can be memory-mapped-- where the I/O device behaves like main memory from the CPU s point of I/O can be instruction-based, where the CPU has a specialized I/O instruction study I/O in detail in chapter 3401 Comp.

6 Org. & Assembly Marie -- Chapter Memory Organization and Memory Organization and AddressingAddressingComputer memory consists of a linear array of addressable storage cells that are similar to can be byte-addressable, or word-addressable, where a word typically consists of two or more is constructed of RAM chips, often referred to in terms of length the memory word size of the machine is 16 bits, then a 4M 16 RAM chip gives us 4 megabytes of 16-bit memory 3401 Comp. Org. & Assembly Marie -- Chapter Memory Organization and Memory Organization and AddressingAddressingHow does the Computer access a memory location corresponds to a particular address?We observe that 4M can be expressed as 22 220= memory locations for this memory are numbered 0 through 222 , the memory bus of this system requires at least 22 address address lines count from 0 to 222- 1 in binary.

7 Each line is either on or off indicating the location of the desired memory 3401 Comp. Org. & Assembly Marie -- Chapter Memory Organization and Memory Organization and AddressingAddressingPhysical memory usually consists of more than one RAM is more efficient when memory is organized into banks of chips with the addresses interleaved across the chipsWith low-order interleaving, the low order bits of the address specify which memory bank contains the address of , in high-order interleaving, the high order address bits specify the memory 3401 Comp. Org. & Assembly Marie -- Chapter Memory Organization and Memory Organization and AddressingAddressingLow-Order InterleavingHigh-Order InterleavingCS 3401 Comp. Org. & Assembly Marie -- Chapter 418 Problem 3 Page 237 Problem 3 Page 237 How many bits would you need to address a 2M 32 memory ifa.

8 The memory is byte-addressable?b. The memory is word-addressable?a. There are 2M 4 bytes which equals 2 220 22= 223total bytes, so 23 bits are needed for an addressb. There are 2M words which equals 2 220= 221, so 21 bits are required for an addressCS 3401 Comp. Org. & Assembly Marie -- Chapter 419 Problem 6 Page 237 Problem 6 Page 237 Suppose that a 2M 16 main memory is built using 256K 8 RAM chips and memory is How many RAM chips are necessary?b. How many RAM chips are there per memory word?c. How many address bits are needed for each RAM chip?d. How many banks will this memory have?e. How many address bits are needed for all of memory?f. If high-order interleaving is used, where would address 14 (which is E in hex) be located?g. Repeat Exercise 6f for low-order 3401 Comp.

9 Org. & Assembly Marie -- Chapter InterruptsThe normal execution of a program is altered when an event of higher-priority occurs. The CPU is alerted to such an event through an can be triggered by I/O requests, arithmetic errors (such as division by zero), or when an invalid instruction is interrupt is associated with a procedure that directs the actions of the CPU when an interrupt occurs. Nonmaskable interrupts are high-priority interrupts that cannot be 3401 Comp. Org. & Assembly Marie -- Chapter MARIEWe can now bring together many of the ideas that we have discussed to this point using a very Simple model model Computer , the Machine Architecture that is Really Intuitive and Easy, MARIE, was designed for the singular purpose of illustrating basic Computer system this system is too Simple to do anything useful in the real world, a deep understanding of its functions will enable you to comprehend system architectures that are much more 3401 Comp.

10 Org. & Assembly Marie -- Chapter MARIEThe MARIE architecture has the following characteristics:Binary, two's complement data program, fixed word length data and words of word-addressable main data instructions, 4 for the opcode and 12 for the 16-bit arithmetic logic unit (ALU).Seven registers for control and data 3401 Comp. Org. & Assembly Marie -- Chapter MARIEMARIE s seven registers are:Accumulator, AC, a 16-bit register that holds a conditional operator ( , "less than") or one operand of a two-operand address register, MAR, a 12-bit register that holds the memory address of an instruction or the operand of an instruction. Memory buffer register, MBR, a 16-bit register that holds the data after its retrieval from, or before its placement in counter, PC, a 12-bit register that holds the address of the next program instruction to be register, IR, which holds an instruction immediatelypreceding its register, InREG, an 8-bit register that holds data read from an input register, OutREG, an 8-bit register, that holds data that is ready for the output 3401 Comp.