14 nm Process Technology: Opening New Horizons

1 14 nm Process technology : Opening New Horizons Mark Bohr intel Senior Fellow Logic technology Development SPCS010 Agenda Introduction 2nd Generation Tri-gate Transistor Logic Area Scaling Cost per Transistor Product Benefits SoC Feature Menu 2 Agenda Introduction 2nd Generation Tri-gate Transistor Logic Area Scaling Cost per Transistor Product Benefits SoC Feature Menu 3 intel technology Roadmap 4 22 nm Manufacturing Development Research 7 nm 10 nm 14 nm intel technology Roadmap 5 22 nm Manufacturing Development Research 7 nm 10 nm 14 nm >500 million chips

2 Using 22 nm Tri-gate (FinFET) transistors shipped to date intel technology Roadmap 6 22 nm Manufacturing Development Research 7 nm 10 nm 14 nm Industry s first 14 nm technology is now in volume manufacturing ~ per generation22 nm32 nm14 nm intel Scaling Trend 7 Scaled transistors provide: Higher performance Lower power Lower cost per transistor Moore s Law continues! How Small is 14 nm? 8 1 1 1 1 10 100 10 100 meter millimeter micrometer nanometer 10 100 10 How Small is 14 nm? 9 1 1 1 1 10 100 10 100 meter millimeter micrometer nanometer 10 100 Fly 7 mm Mite 300 um Virus 100 nm Blood Cell 7 um Silicon Atom nm Mark m 10 How Small is 14 nm?

3 10 Very small 1 1 1 1 10 100 10 100 meter millimeter micrometer nanometer 10 100 Fly 7 mm Mite 300 um Virus 100 nm Blood Cell 7 um Silicon Atom nm Mark m 10 14 nm Process 14 nm Tri-gate Transistor Fins 11 8 nm Fin Width 42 nm Fin Pitch Si Substrate Gate 14 nm intel Core M Processor 12 Industry s first 14 nm processor now in volume production billion transistors 82 mm2 die size Agenda Introduction 2nd Generation Tri-gate Transistor Logic Area Scaling Cost per Transistor Product Benefits SoC Feature Menu 13 Minimum Feature Size 14 intel has developed a true 14 nm technology with good dimensional scaling 22 nm 14 nm Scale Transistor Fin Pitch 60 42.

4 70x Transistor Gate Pitch 90 70 .78x Interconnect Pitch 80 52 .65x nm nm Si Substrate 60 nm pitch 34 nm height Si Substrate Transistor Fin Optimization 15 22 nm Process 14 nm Process Si Substrate 60 nm pitch 34 nm height Si Substrate 42 nm pitch Transistor Fin Optimization 16 Tighter fin pitch for improved density 22 nm Process 14 nm Process Si Substrate 60 nm pitch 34 nm height Si Substrate 42 nm pitch 42 nm height Transistor Fin Optimization 17 Taller and thinner fins for improved performance 22 nm Process 14 nm Process Si Substrate 60 nm pitch 34 nm height Si Substrate 42 nm pitch 42 nm height Transistor

5 Fin Optimization 18 Reduced number of fins for improved density and lower capacitance 22 nm Process 14 nm Process Si Substrate Metal Gate Si Substrate Metal Gate Transistor Fin Optimization 19 22 nm Process 14 nm Process 1st generation Tri-gate 2nd generation Tri-gate Transistor Fin Optimization 20 22 nm Process 14 nm Process 1st generation Tri-gate 2nd generation Tri-gate Interconnects 21 52 nm interconnect pitch provides better than normal interconnect scaling 80 nm minimum pitch 52 nm ( ) minimum pitch 22 nm Process 14 nm Process SRAM Memory Cells 22 14 nm design rules + 2nd generation Tri-gate provides industry-leading SRAM density.

6 108 um2 (Used on CPU products) .0588 um2 ( ) 22 nm Process 14 nm Process Agenda Introduction 2nd Generation Tri-gate Transistor Logic Area Scaling Cost per Transistor Product Benefits SoC Feature Menu 23 1010045 nm32 nm22 nm14 nm10 nmGate Pitch(nm) technology Node~ per generationTransistor Gate Pitch Scaling 24 Gate pitch scaling ~ for good balance of performance, density and low leakage 1010045 nm32 nm22 nm14 nm10 nmMetal Pitch(nm) technology Node~ per generationMetal Interconnect Pitch Scaling 25 14 nm interconnects scaling faster than normal for improved density Logic Cell Height Logic Cell Width Gate Pitch Metal Pitch Logic Area Scaling Metric 26 Logic area scaling ~ gate pitch x metal pitch 10001000045/40 nm32/28 nm22/20 nm16/14 nm10 nmGate PitchxMetal Pitch(nm2) technology NodeIntel~ per generationLogic Area Scaling 27 Logic area continues to scale ~ per generation 10001000045/40 nm32/28 nm22/20 nm16/14 nm10 nmGate PitchxMetal Pitch(nm2)

7 technology NodeIntelOthersLogic Area Scaling 28 In the past, others tended to have better density, but came later than intel 45nm: K-L Cheng (TSMC), 2007 IEDM, p. 243 28nm: F. Arnaud (IBM alliance), 2009 IEDM, p. 651 20nm: H. Shang (IBM alliance), 2012 VLSI, 10001000045/40 nm32/28 nm22/20 nm16/14 nm10 nmGate PitchxMetal Pitch(nm2) technology NodeIntelOthersLogic Area Scaling 29 intel continues scaling at 14 nm while other pause to develop FinFETs 45nm: K-L Cheng (TSMC), 2007 IEDM, p. 243 28nm: F. Arnaud (IBM alliance), 2009 IEDM, p. 651 20nm: H.

8 Shang (IBM alliance), 2012 VLSI, 16nm: S. Wu (TSMC), 2013 IEDM, p. 224 10nm: K-I Seo (IBM alliance), 2014 VLSI, p. 14 10001000045/40 nm32/28 nm22/20 nm16/14 nm10 nmGate PitchxMetal Pitch(nm2) technology Node1stFinFET2ndFinFETP lanar1stFinFETI ntelOthersLogic Area Scaling 30 intel is shipping its 2nd generation FINFETs before others ship their 1st generation 45nm: K-L Cheng (TSMC), 2007 IEDM, p. 243 28nm: F. Arnaud (IBM alliance), 2009 IEDM, p. 651 20nm: H. Shang (IBM alliance), 2012 VLSI, 16nm: S. Wu (TSMC), 2013 IEDM, p. 224 10nm: K-I Seo (IBM alliance), 2014 VLSI, p.

9 14 10001000045/40 nm32/28 nm22/20 nm16/14 nm10 nmGate PitchxMetal Pitch(nm2) technology NodeQ4 11Q2 141H 142015?IntelOthersLogic Area Scaling 31 intel 14 nm is both denser and earlier than what others call 16nm or 14nm 45nm: K-L Cheng (TSMC), 2007 IEDM, p. 243 28nm: F. Arnaud (IBM alliance), 2009 IEDM, p. 651 20nm: H. Shang (IBM alliance), 2012 VLSI, 16nm: S. Wu (TSMC), 2013 IEDM, p. 224 10nm: K-I Seo (IBM alliance), 2014 VLSI, p. 14 Agenda Introduction 2nd Generation Tri-gate Transistor Logic Area Scaling Cost per Transistor Product Benefits SoC Feature Menu 32 110100130 nm90 nm65 nm45 nm32 nm22 nm14 nm10 nm$ / mm2(normalized)Cost per Transistor 33 Wafer cost is increasing due to added masking steps 110100130 nm90 nm65 nm45 nm32 nm22 nm14 nm10 nm$ / mm2(normalized)Cost per Transistor 34 14 nm achieves better than normal area scaling nm90 nm65 nm45 nm32 nm22 nm14 nm10 nmmm2/ Transistor(normalized)110100130 nm90 nm65 nm45 nm32 nm22 nm14 nm10 nm$ / mm2(normalized)

10 Nm90 nm65 nm45 nm32 nm22 nm14 nm10 nmmm2/ Transistor(normalized) nm90 nm65 nm45 nm32 nm22 nm14 nm10 nm$ / Transistor(normalized)Cost per Transistor 35 intel 14 nm continues to deliver lower cost per transistor Agenda Introduction 2nd Generation Tri-gate Transistor Logic Area Scaling Cost per Transistor Product Benefits SoC Feature Menu 36 Transistor Performance vs. Leakage 37 14 nm transistors provide improved performance and leakage .. nm22 nm32 nm45 nm65 nmLower Leakage PowerHigher Transistor Performance (switching speed)Transistor Performance vs.