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2-Port USB 3.0 Hub Reference Design - TI.com

VTI HubReferenceDesignTI DesignsDesignFeaturesTI Designsprovidethe foundationthat you needThe TIDA-00287is a fully ,testingand designfiles tohub:quicklyevaluateand customizethe Designs Supportsindividualport powercontrolhelpyouaccelerateyourtime to market. ESDprotectionon bothupstreamand downstreamportsDesignResources Operatesas a bus-powereddevice(all powerIEC ESDP rotectionDiodesTPD6E05U06beingsuppliedby the upstreamhost or hub)TUSB8020B2-PortUSBHub Supportsoperationas a and Computersystems DockingstationsASKOur AnalogExperts MonitorsWEBENCH CalculatorTools Set-topboxesspacer1spacer1spacer1spacer1 spacer1spacer1spacer1spacer1spacer1space r1spacer1spacer1spacer1spacer1spacer2spa cer1spacer3spacer1spacer4spacer2spacer5s pacer3spacer4spacer5An IMPORTANTNOTICEat the end of this TI referencedesignaddressesauthorizeduse, intellectualpropertymattersand otherimportantdisclaimersand trademarksare the propertyof Hub ReferenceDesignSubmitDocumentationFeedba ckCopyright 2014, Hub Designis a providessimultaneousSuperSpeedandhigh-sp eed/full-speedconnectionson the upstreamport and providesSuperSpeed,high-speed,full-speed .

3.3 V 1.1 V Circuit Description www.ti.com 1 Circuit Description The USB 3.0 Hub Design is a two-port USB 3.0 compliant hub. It provides simultaneous SuperSpeed and

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Transcription of 2-Port USB 3.0 Hub Reference Design - TI.com

1 VTI HubReferenceDesignTI DesignsDesignFeaturesTI Designsprovidethe foundationthat you needThe TIDA-00287is a fully ,testingand designfiles tohub:quicklyevaluateand customizethe Designs Supportsindividualport powercontrolhelpyouaccelerateyourtime to market. ESDprotectionon bothupstreamand downstreamportsDesignResources Operatesas a bus-powereddevice(all powerIEC ESDP rotectionDiodesTPD6E05U06beingsuppliedby the upstreamhost or hub)TUSB8020B2-PortUSBHub Supportsoperationas a and Computersystems DockingstationsASKOur AnalogExperts MonitorsWEBENCH CalculatorTools Set-topboxesspacer1spacer1spacer1spacer1 spacer1spacer1spacer1spacer1spacer1space r1spacer1spacer1spacer1spacer1spacer2spa cer1spacer3spacer1spacer4spacer2spacer5s pacer3spacer4spacer5An IMPORTANTNOTICEat the end of this TI referencedesignaddressesauthorizeduse, intellectualpropertymattersand otherimportantdisclaimersand trademarksare the propertyof Hub ReferenceDesignSubmitDocumentationFeedba ckCopyright 2014, Hub Designis a providessimultaneousSuperSpeedandhigh-sp eed/full-speedconnectionson the upstreamport and providesSuperSpeed,high-speed,full-speed .

2 Or low-speedconnectionson the hub designprovidespowercontrolforeachdownstr eamport and overcurrentprotection2 Theoryof OperationA blockdiagramof the designin Figure1 showsa Hub with a TypeA plug upstreamport andtwo TypeA the designis shownas well as ESDprotectionelementson the upstreamand downstreamsidesof the currentlimitingis providedby two TPS2553(AdjustableCurrent-LimitedPower-D istributionSwitch) TUSB8020 Bis a two port providesSuperSpeedand high/fullspeedconnectionson the also supportsSuperSpeed,high/fullspeedor low-speedconnectionson the upstreamport is connectedto an environmentthat supportsonlyhigh-speedor full-speed/low-speedconnections,SuperSpe edis disabledon the upstreamport is connectedto an environmentthat supportsonly full-speed/low-speedconnections,SuperSpe edand high-speedare bothdisabledon the hub supportsovercurrentprotectionand batterychargingas well as eithergangedswitchingor perport hub is configuredwith the de-assertionof Table1 for the TUSB8020 BPower-onResetSettingsTUSB8020 BFunctionStatusDownstreamport powermanagementEnabledPowercontrolsignal polaritySignalsare activehighPowerport Hub ReferenceDesignTIDU428 November2014 SubmitDocumentationFeedbackCopyright 2014,TexasInstrumentsIncorporatedACTIVE HIGH ENABLE.

3 THIS SETS THE CURRENTLIMIT TO (TYP)FLT_PORT1#EN_PORT1 VBUS_OUT_PORT_1 BOARD_5 VEN_PORT1[P3]FLT_PORT1# [P3]VBUS_OUT_PORT_1 [P4]C4922uF0603U17 TPS2553 SOT23_6IN1 GND2EN3 FAULT# + V+ mainpoweron the boardis 5 V and is suppliedby the showstheconfigurationof the board s 5 V comingfromthe upstreamUSBport is regulateddownto V througha LM3674switchingregulatoris usedto the corevoltageto the 5-V poweris also passedto the TPS2553current-limitingswitchesthat supplypowerto the downstreamportsis providedby two TPS2553(AdjustableCurrent-LimitedPower-D istributionSwitch).Theseswitchesare controlledby the USBhub chip,and haveadjustablecurrentlimitson the designis set for a currentlimit of (typical).Figure3. DownstreamPowerDelivery3 ComponentSelectionAll componentscontainedin this designare chosento providea low-costsolutionwhenpurchasedinlargequan tities,whileminimizingcomponentcountand maintainingperformanceto satisfythe TUSB8020 Bwas chosenas a low cost 2 port and forbothupstreamand be supportedas can be per-portor OTPROMis includedfor custom3rd partyVID/PIDand no specialdriversrequiredfor this Hub ReferenceDesignSubmitDocumentationFeedba ckCopyright @ LDO - designusestwo can be set by an deliver~900mA.

4 Itshouldbe notedthat portscan supplyfar in excessof the port that the hub is pluggedinto can providein excessof A, thenbothdownstreamportswill supportthe full 900 mA of all USBportsis suppliedby the part providesESDprotectionfor 3 differentialpairsat dataspeedsof up to 6 GBpsand has low capacitanceof pF. EachUSBport usesone of thesepartsto protectthe packageallowsforstraightthroughroutingan dis placedas closeto the USBconnectoras ESDprotectionis mainpowerfor the boardis +5 V. This is suppliedfromthe upstreamUSBport voltagesforthe hub are generatedfrom2 (TLV70033)takesthe BOARD_5 Vand regulatesitdownto V (referto Figure4). The TLV70033is an LDOthat is capableof supplying200 mA. U22(LM3674)generatesthe usedfor the showsschematicsof the powersupplycircuitryfor the circuitwas designedusingTI s WebenchDesignTool,and selectedfor the smallPCBfootprintand low TUSB8020 BPowerSupply(TLV70033)Figure5.

5 TUSB8020 BPowerSupply(LM3674) Hub ReferenceDesignTIDU428 November2014 SubmitDocumentationFeedbackCopyright 2014, PCBstack-updesignwas chosento accommodatethe 90- impedanceof mils and differentialpair spacingof 5 mils is usedwith this tracesareroutedon the top side of the boardand referencesa solidgroundplanethat is layer2. Layer3 is thepowerlayerand includesthe 5- and bottomside,layer4, is wherethe well as all simplifythe assemblyprocess,all componentsare placedon the topside of the throughFigure11 showthe layoutfor all 4 layersas welllas the silk screensFigure6. Top Layer Routes5 TIDU428 Hub ReferenceDesignSubmitDocumentationFeedba ckCopyright 2014, Layer2 GroundPlaneFigure8. Layer3 PowerPlane(+5 V and + ) Hub ReferenceDesignTIDU428 November2014 SubmitDocumentationFeedbackCopyright 2014, BottomSide- + RoutingFigure10. Top SideSilk Screen7 TIDU428 Hub ReferenceDesignSubmitDocumentationFeedba ckCopyright 2014, BottomSideSilk and linesmustbe routedas controlledimpedance, use of vias and 90 degreecornersin the routingof the high-speedlinesreferencea solidgroundplaneand the planeis void of cuts and splitsto be placedin-linewith the high-speedsignaltracestoreducereflection scausedby showsthe PCBstack-upusedfor the Hub ReferenceDesignTIDU428 November2014 SubmitDocumentationFeedbackCopyright 2014, MeasuredPerformance5 Verificationand DownstreamPort1 Figure13.

6 DownstreamSignalQualityEye Diagram- Port1 Figure14. DownstreamSignalQualityPlot - Port19 TIDU428 Hub ReferenceDesignSubmitDocumentationFeedba ckCopyright 2014,TexasInstrumentsIncorporatedVerific ationand DownstreamPort2 Figure15. DownstreamSignalQualityEye Diagram- Port2 Figure16. DownstreamSignalQualityPlot - Hub ReferenceDesignTIDU428 November2014 SubmitDocumentationFeedbackCopyright 2014, DownstreamPort1 withoutESDP rotectionFigure17. DownstreamSignalQualityEye Diagram- Port1 WithoutESDP rotectionDeviceFigure18. DownstreamSignalQualityPlot - Port1 WithoutESDP rotectionDevice11 TIDU428 Hub ReferenceDesignSubmitDocumentationFeedba ckCopyright 2014,TexasInstrumentsIncorporatedVerific ationand DownstreamPort2 withoutESDP rotectionFigure19. DownstreamSignalQualityEye Diagram- Port2 WithoutESDP rotectionDeviceFigure20. DownstreamSignalQualityPlot - Port2 Hub ReferenceDesignTIDU428 November2014 SubmitDocumentationFeedbackCopyright 2014, DownstreamPort1 Figure21.

7 DownstreamCP1 Eye Diagram- Port1 Figure22. DownstreamCP0 Eye Diagram- Port113 TIDU428 Hub ReferenceDesignSubmitDocumentationFeedba ckCopyright 2014,TexasInstrumentsIncorporatedVerific ationand DownstreamPort2 Figure23. DownstreamCP1 Eye Diagram- Port2 Figure24. DownstreamCP0 Eye Diagram- Hub ReferenceDesignTIDU428 November2014 SubmitDocumentationFeedbackCopyright 2014, VI(mA)Rk sectiondiscussesdifferentdesignoptionsth at wereevaluatedfor this projectto give the designerflexibilityto modifythe chosethe TPD6E05U06part to provideESDprotectionon this was also chosendue to itssmallsize,capabilityto provideprotectionof up to 3 differentialpairs,and low using3 singlepackagepartsfor eachUSBconnector(TPD2 EUSB30).This allowsmoreflexibilityin TUSB8020 Bhas an interfacefor an optionalI2C EEPROMor can be usedforstoringvendorinformationand I2C EEPROM like the AT24C04or aSMBUS host can be connectedto the serialinterfacefor this purpose,but is not a designa 24-MHzfundamentalfrequencycrystalwas usedto generatethe clock(CTSF requencyControls#445C25D24M00000).

8 Optionally,a 24-MHzoscillatorcan be usedand connectedto XI pin (pin38). Table2 lists the optionsfor the TUSB8020 Bthat are set at the risingedgeof the Grst#pin (pin 11).Table2. Power-onResetOptionsSignalName(Pin #)DefaultConditionSMBUSz/SS_DN2(pin 22)Pull-Up0 = SMBbusenabled1 = I2C enabledFPMGT/SMBA1/SS_UP(pin 36)Pull-Up0 = downstreampowerswitchingsupported1 = downstreampowerswitchnot supportedPWRCTL_POL/SS_DN1(pin 21)Pull-Down0 = PWRCTL polarityis activehigh1 = PWRCTL polarityis activelowGANGED/SMBA2/HS_UP(pin 35)Pull-Up0 = Individualport powercontrolsupported1 = GangedpowercontrolsupportedPWRCTL/BATEN( pins4 and 6)Pull-Down0 = Batterychargingnot supported1 = has manyoptionsfor providingpowerto the referencedesign,the TPS2553is usedto part has an adjustablecurrentlimit that is controlledby is usedto set the currentlimit on downstreamport 1, and R25 for port 2. Theequationusedto calculatethe currentlimit is as follows:(1) V for corelogicand V for I/O currentrequirementscan beseenin the datasheet(SLLSEF6), and TI has V has a low-powerrequirement,a low-cost,low-component-countLDOwas usedto step downthe BOARD_5 Vto V.

9 Is generatedby an LM3674 step Hub ReferenceDesignSubmitDocumentationFeedba ckCopyright 2014, 1 PORT 25 VVBUS_OUT_1 VBUS_OUT_1 VBUS_OUT_2 TUSB8020B BLOCK DIAGRAMPage 2 Page 3 Page 4 Page 4 Page 5 Page 6 UPSTREAMUSB PORTDOWNSTREAMPORT 1 DOWNSTREAMPORT 2 TPS2553 TPS25535 VVBUS_OUT_2 Page throughFigure30 illustratethe electricalschematicsfor the Schematic(1 of 6) Hub ReferenceDesignTIDU428 November2014 SubmitDocumentationFeedbackCopyright 2014,TexasInstrumentsIncorporatedUSB TYPE-A PLUG CONNECTOR(RIGHT ANGLE) TYPE-A UPSTREAM CONNECTORROUTE THESE LINES ON THE TOP SIDE ONLYKEEP CAPS CLOSE TO CONNECTORVBUS_PUP_FBSSTXM_PUPSSTXP_PUPBO ARD_5 VDM_UP [P3]DP_UP [P3]SSTXM_UP [P3]SSTXP_UP [P3]SSRXM_UP [P3]SSRXP_UP [P3] +14D1-13D2+12D2-11D3+ @ 100 MHZ, Schematic(2 of 6)17 TIDU428 Hub ReferenceDesignSubmitDocumentationFeedba ckCopyright 2014,TexasInstrumentsIncorporatedTUSB 2 PORT HUBUPSTREAM PORTDOWNSTREAM PORTSXIXOGRST#SSTXP_UPSSTXM_UPSSRXP_UPSS RXM_UPDP_UPDM_UPUSB_VBUS_UPSSTXP_DN1 SSTXM_DN1 SSRXP_DN1 SSRXM_DN1DP_DN1DM_DN1EN_PORT1 FLT_PORT1#SSTXP_DN2 SSTXM_DN2 SSRXP_DN2 SSRXM_DN2DP_DN2DM_DN2EN_PORT2 FLT_PORT2#PWRCTL_POLGANGEDUSB_R1I2C_SDAI 2C_SCLPWR_MGMT_EN#TESTBOARD_1P1 VBOARD_3P3 VBOARD_1P1 VBOARD_3P3 VBOARD_3P3 VBOARD_5 VSSTXP_UP[P2]SSTXM_UP[P2]DP_UP[P2]DM_UP[ P2]SSRXP_DN1 [P4]SSRXM_DN1 [P4]FLT_PORT1# [P5]SSTXP_DN1 [P4]SSTXM_DN1 [P4]EN_PORT1 [P5]DM_DN1 [P4]DP_DN1 [P4]SSTXP_DN2 [P4]SSTXM_DN2 [P4]SSRXP_DN2 [P4]SSRXM_DN2 [P4]DP_DN2 [P4]DM_DN2 [P4]FLT_PORT2# [P5]EN_PORT2 [P5]SSRXP_UP[P2]SSRXM_UP[P2]

10 , #11 USB_SSTXP_UP29 USB_SSTXM_UP28 USB_SSRXP_UP32 USB_SSRXM_UP31 USB_DP_UP26 USB_DM_UP27 USB_R124 USB_VBUS9 USB_SSTXP_DN143 USB_SSTXM_DN144 USB_SSRXP_DN146 USB_SSRXM_DN147 USB_DP_DN141 USB_DM_DN142 PWRCTL1/BATEN14 OVERCURZ15 USB_SSTXP_DN216 USB_SSTXM_DN217 USB_SSRXP_DN219 USB_SSRXM_DN220 USB_DP_DN214 USB_DM_DN215 PWRCTL2/BATEN26 OVERCURZ28 SCL/SMBCLK2 SDA/SMBDAT3 SMBUSz/SS_DN222 FPMGT/SMBA1/SS_UP36 PWRCTL_POL/SS_DN121 GANGED/SMBA2 Schematic(3 of 6) Hub ReferenceDesignTIDU428 November2014 SubmitDocumentationFeedbackCopyright 2014,TexasInstrumentsIncorporatedSINGLE USB CONNECTORKEEP CAPS CLOSE TO CONNECTORKEEP CAPS CLOSE TO CONNECTORSINGLE USB CONNECTORDOWNSTREAM USB ports 1&2 PORT 1 PORT 2 VBUS_P1_FBSSRXM_DN1 SSRXP_DN1 HUB_SSTXP_P1 HUB_SSTXM_P1 VBUS_P2_FBSSRXM_DN2 SSRXP_DN2 HUB_SSTXP_P2 HUB_SSTXM_P2 VBUS_OUT_PORT_1 [P5]DM_DN1 [P3]DP_DN1 [P3]SSTXM_DN1 [P3]SSTXP_DN1 [P3]VBUS_OUT_PORT_2 [P5]DM_DN2 [P3]DP_DN2 [P3]SSTXM_DN2 [P3]SSTXP_DN2 [P3]SSRXM_DN1 [P3]SSRXP_DN1 [P3]SSRXM_DN2 [P3]SSRXP_DN2 [P3]FB5220 @ 100 MHZ,2A0603FB4220 @ 100 MHZ, +14D1-13D2+12D2-11D3+9D3-8 GND55 GND1010NC11NC22NC33NC44NC66NC77J5 USB3_TYPEA_CONNECTERCON_THRT_USB3A_F3 VBUS1DM2DP3 GND4 SSRXN5 SSRXP6 GND7 SSTXN8 SSTXP9 SHIELD010 SHIELD111 SHLD212 SHLD313U20 TPD6E05U06 UQFN_14_142X57_20D1+14D1-13D2+12D2-11D3+ Schematic(4 of 6)


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