256 10 FPGA IP Design Example User Guide - …

1 External Memory Interfaces Intel Cyclone 10 GX FPGA IP DesignExample User GuideUpdated for Intel Quartus Prime Design Suite: FeedbackUG-20119 | document on the web: PDF | HTMLC ontents1. Design Example Quick Start Guide for External Memory Interfaces Intel Cyclone 10 GX FPGA IP .. Creating an EMIF Generating and Configuring the EMIF Intel Cyclone 10 GX EMIF Parameter Editor Generating the Synthesizable EMIF Design Generating the EMIF Design Example for Simulation Versus Hardware Simulating External Memory Interface IP With Pin Placement for Intel Cyclone 10 GX EMIF Compiling and Programming the Intel Cyclone 10 GX EMIF Design Debugging the Intel Cyclone 10 GX EMIF Design 152.

2 Design Example Description for External Memory Interfaces Intel Cyclone 10 GXFPGA IP .. Synthesis Example Simulation Example Example Designs Interface Document Revision History for External Memory Interfaces Intel Cyclone 10 GXFPGA IP Design Example User 21 ContentsExternal Memory Interfaces Intel Cyclone 10 GX FPGA IP Design ExampleUser GuideSend Feedback21. Design Example Quick Start Guide for External MemoryInterfaces Intel Cyclone 10 GX FPGA IPA new interface and more automated Design Example flow is available for Intel Cyclone 10 GX external memory Example Designs tab in the parameter editor allows you to specify the creationof synthesis and/or simulation file sets which you can use to validate your EMIF can generate an Example Design specifically for an Intel FPGA development kit.

3 Orfor any EMIF IP that you Design Example WorkflowsExampleDesignGenerationCompilat ion(Simulator)FunctionalSimulationCompil ation(Quartus Prime)HardwareTesting Design Example Timing Analysis(Quartus Prime)Figure an EMIF Example Design With an Intel Cyclone 10 GXDevelopment KitUG-20119 | FeedbackIntel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/or othercountries.

4 Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.

5 *Other names and brands may be claimed as the property of Creating an EMIF ProjectFor the Intel Quartus Prime software version and later, you must create an IntelQuartus Prime project before generating the EMIF IP and Design the Intel Quartus Prime software and select File New Project Specify a directory and name for the project that you want to create. Click Verify that Empty Project is selected. Click Next two Design Example Quick Start Guide for External Memory Interfaces Intel Cyclone 10 GXFPGA IPUG-20119 | Memory Interfaces Intel Cyclone 10 GX FPGA IP Design ExampleUser GuideSend Feedback44.

6 Under Name filter, type the device part Under Available devices, select the appropriate Click Design Example Quick Start Guide for External Memory Interfaces Intel Cyclone 10 GXFPGA IPUG-20119 | FeedbackExternal Memory Interfaces Intel Cyclone 10 GX FPGA IP Design ExampleUser Generating and Configuring the EMIF IPThe following steps illustrate how to generate and configure the EMIF IP. The steps aresimilar regardless of the memory protocol that you are In the IP Catalog window, select Intel Cyclone 10 External MemoryInterfaces.

7 (If the IP Catalog window is not visible, select View UtilityWindows IP Catalog.)2. In the IP Parameter Editor, provide an entity name for the EMIF IP (the namethat you provide here becomes the file name for the IP) and specify a The parameter editor has multiple tabs where you must configure parameters toreflect your EMIF implementation:1. Design Example Quick Start Guide for External Memory Interfaces Intel Cyclone 10 GXFPGA IPUG-20119 | Memory Interfaces Intel Cyclone 10 GX FPGA IP Design ExampleUser GuideSend Intel Cyclone 10 GX EMIF Parameter Editor GuidelinesTable Parameter Editor GuidelinesParameter Editor TabGuidelinesGeneralEnsure that the following parameters are entered correctly: The speed grade for the device.

8 The memory clock frequency. The PLL reference clock Refer to the data sheet for your memory device to enter the parameters onthe Memory I/O For initial project investigations, you may use the default settings on theMem I/O tab. For advanced Design validation, you should perform board simulation toderive optimal termination I/O For initial project investigations, you may use the default settings on theFPGA I/O tab. For advanced Design validation, you should perform board simulation withassociated IBIS models to select appropriate I/O Timing For initial project investigations, you may use the default settings on theMem Timing tab.

9 For advanced Design validation, you should enter parameters according toyour memory device's data For initial project investigations, you may use the default settings on theBoard tab. For advanced Design validation and accurate timing closure, you shouldperform board simulation to derive accurate intersymbol interference (ISI)/crosstalk and board and package skew information, and enter it on theBoard the controller parameters according to the desired configuration andbehavior for your memory can use the parameters on the Diagnostics tab to assist in testing anddebugging your memory DesignsThe Example Designs tab lets you generate Design examples for synthesisand for simulation.

10 The generated Design Example is a complete EMIF systemconsisting of the EMIF IP and a driver that generates random traffic to validatethe memory detailed information on individual parameters, refer to the appropriate chapter foryour memory protocol in the Intel Cyclone 10 GX External Memory Interfaces IP Generating the Synthesizable EMIF Design ExampleFor the Intel Cyclone 10 GX development kits, there are presets that automaticallyparameterize the EMIF IP and generate pinouts for the specific Verify that the Presets window is visible.