256 10 L- and H-Tile Transceiver PHY User Guide

1 Intel Stratix 10 L- and H-TileTransceiver PHY User GuideSubscribeSend FeedbackUG-20055 | document on the web: PDF | HTMLC ontents1. L-Tile/ H-Tile Layout in Intel Stratix 10 Device Intel Stratix 10 GX/SX H-Tile Intel Stratix 10 TX H-Tile and E-Tile Intel Stratix 10 MX H-Tile and E-Tile L-Tile/ H-Tile Counts in Intel Stratix 10 Devices and Package L-Tile/ H-Tile Building Transceiver Bank Transceiver Channel GX and GXT Channel Placement GXT Channel PLL and Clock Ethernet Hard PCIe Gen1/Gen2/Gen3 Hard IP Overview Revision Implementing the Transceiver PHY Layer in L- Transceiver Design IP Transceiver Design Select the PLL IP Reset Controller .. Create Reconfiguration Connect the Native PHY IP Core to the PLL IP Core and Reset Connect Datapath .. Modify Native PHY IP Core Compile the Verify Design Configuring the Native PHY IP Protocol GXT General and Datapath Parameters.

2 PMA PCS-Core Interface Analog PMA Settings Enhanced PCS Parameters .. Standard PCS PCS Direct Datapath Dynamic Reconfiguration Generation Options PMA, Calibration, and Reset PCS-Core Interface Enhanced PCS Standard PCS Transceiver PHY PCS-to-Core Interface Reference Port IP Core File Using the Intel Stratix 10 L-Tile/ H-Tile Transceiver Native PHY Intel Stratix 10 FPGAIP 104 ContentsIntel Stratix 10 L- and H-Tile Transceiver PHY User GuideSend PMA PCS Deterministic Latency Use Debug Implementing the PHY Layer for Transceiver PCI Express (PIPE).. Unused Transceiver Simulating the Native PHY IP How to Specify Third-Party RTL Simulators .. Scripting IP Custom Simulation Implementing the Transceiver Native PHY Layer in L-Tile/ H-Tile Revision PLLs and Clock ATX CMU Input Reference Clock Dedicated Reference Clock Receiver Input PLL Cascading as an Input Reference Clock Reference Clock Core Clock as an Input Reference Transmitter Clock x1 Clock x6 Clock x24 Clock GXT Clock Clock Generation FPGA Fabric- Transceiver Interface Double Rate Transfer Transmitter Data Path Interface Receiver Data Path Interface Channel PMA PMA and PCS Selecting Channel Bonding Skew PLL Cascading Clock Using PLLs and Clock Non-bonded Bonded Implementing PLL Mix and Match PLLs and Clock Networks Revision FeedbackIntel Stratix 10 L- and H-Tile Transceiver PHY User Guide34.

3 Resetting Transceiver When Is Reset Required? .. Transceiver PHY Reset Controller Intel Stratix 10 FPGA IP How Do I Reset?.. Recommended Reset Transceiver Blocks Affected by Reset and Power-down Using PCS Reset Status Using Transceiver PHY Reset Controller Intel Stratix 10 FPGA Parameterizing Transceiver PHY Reset Controller Intel Stratix 10 FPGA Transceiver PHY Reset Controller Intel Stratix 10 FPGA IP Transceiver PHY Reset Controller Intel Stratix 10 FPGA IP Transceiver PHY Reset Controller Intel Stratix 10 FPGA IP Resource Using a User-Coded Reset User-Coded Reset Controller Combining Status or PLL Lock Signals with User Coded Reset Resetting Transceiver Channels Revision Intel Stratix 10 L-Tile/ H-Tile Transceiver PHY PMA Transmitter Receiver Enhanced PCS Transmitter Receiver RX KR FEC Intel Stratix 10 Standard PCS Transmitter Receiver Intel Stratix 10 PCI Express Gen3 PCS Transmitter Receiver PIPE PCS Support for GXT Square Wave PRBS

4 Pattern PRBS Pattern Loopback Intel Stratix 10 L-Tile/ H-Tile Transceiver PHY Architecture Revision Reconfiguration Interface and Dynamic Reconfiguring Channel and PLL Interacting with the Reconfiguration Reading from the Reconfiguration Writing to the Reconfiguration Multiple Reconfiguration Configuration Embedded Reconfiguration Recommendations for Dynamic Steps to Perform Dynamic Channel Stratix 10 L- and H-Tile Transceiver PHY User GuideSend PLL Direct Reconfiguration Native PHY IP or PLL IP Core Guided Reconfiguration Reconfiguration Flow for Special Switching Transmitter Switching Reference Reconfiguring Between GX and GXT Changing Analog PMA Ports and Dynamic Reconfiguration Interface Merging Across Multiple IP Embedded Debug Altera Debug Master Endpoint (ADME).. Optional Reconfiguration Timing Closure Unsupported Transceiver Register Reconfiguration Interface and Dynamic Revision 4287.

5 Reconfiguration Interface and Arbitration with PreSICE (Precision Signal IntegrityCalibration Engine).. Calibration Avalon-MM Interface Arbitration User Recalibration Enable Capability Rate Switch Flag Power-up Background User Recalibrating a Duplex Channel (both PMA TX and PMA RX).. Recalibrating the PMA RX Only in a Duplex Recalibrating the PMA TX Only in a Duplex Recalibrating a PMA Simplex RX without a Simplex TX Merged into theSame Physical Recalibrating a PMA Simplex TX without a Simplex RX Merged into theSame Physical Recalibrating Only a PMA Simplex RX in a Simplex TX Merged Recalibrating Only a PMA Simplex TX in a Simplex RX Merged Recalibrating the Recalibrating the ATX Recalibrating the CMU PLL when it is Used as a TX Calibration Revision Logical View of the L-Tile/ H-Tile Transceiver ATX_PLL Logical Register ATX PLL Optional Reconfiguration Logic ATX PLL- Optional Reconfiguration Logic ATX PLL- Control & Embedded Streamer (ATX PLL).

6 CMU_PLL Logical Register FeedbackIntel Stratix 10 L- and H-Tile Transceiver PHY User CDR/CMU and PMA Optional Reconfiguration Logic CMU PLL- Optional Reconfiguration Logic CMU PLL- Control & Embedded Streamer (CMU PLL).. FPLL Logical Register fPLL Optional Reconfiguration Logic Optional Reconfiguration Logic fPLL-Control & Embedded Streamer (fPLL).. Channel Logical Register Transmitter PMA Logical Register Receiver PMA Logical Register Pattern Generators and Optional Reconfiguration Logic PHY- Optional Reconfiguration Logic PHY- Control & Embedded Streamer (Native PHY).. Static Polarity CDR/CMU and PMA Logical View Register Map of the L-Tile/ H-Tile Transceiver Registers Revision 468 ContentsIntel Stratix 10 L- and H-Tile Transceiver PHY User GuideSend Feedback61. OverviewIntel Stratix 10 devices offer up to 144 transceivers with integrated advanced high-speed analog signal conditioning and clock data recovery circuits for chip-to-chip,chip-to-module, and backplane Intel Stratix 10 devices contain a combination of GX, GXT, or GXE channels, inaddition to the hardened IP blocks for PCI Express* and Ethernet Intel Stratix 10 device introduces several Transceiver tile variants to support awide variety of protocol implementations.

7 These Transceiver tile variants are L-Tiles, H-Tiles, and E-Tiles. This user Guide describes both the L- and H-Tile Tile Variants Comparison of Transceiver CapabilitiesFeatureGX/SX L-TileTransceiversGX/SX H-TileTransceiversTX/MXE-Tile and H-Tile TransceiversMaximumDatarate(Chip-to-chip )GX (1) GbpsGX GbpsGXT GbpsGXE Gbps PulseAmplitude Modulation-4(PAM-4)GXE 30 Gbps Non-return to zero (NRZ)GXT (1) GbpsMaximumDatarate(Backplane)GX and GXT GX channels/device32 GXT channels/device (eight pertile)96 GX channels/device64 GXT channels/device (16 per tile)144 GX channels/device16 GXT channels/device60 GXE channels/device(PAM-4 @ 56 Gbps) or 120channels/device (PAM-4 @ 30 Gbps)144 GX channels/device30 GXT channels/device120 GXE channels/device(NRZ @ 30 Gbps)Hard IPPCIe Gen3 x16 upto four per device50/100 GbE MAC up tofour per devicePCIe Gen3 x16 up tofour per deviceSR-IOV (four PF/2 KVF)100 GbE MAC & RS (528, 514)

8 -FEC up to 20 per device10/25 GbE MAC and RS (528, 514)-FEC up to 120 perdeviceKP-FEC, up to 20 per devicePCIe Gen3 x16 up to 2 per device ( H-Tile only)SR- IOV (4 PF 2K VF each device H-Tile only)In all Intel Stratix 10 devices, the various Transceiver tiles connect to the FPGA fabricusing Intel EMIB (Embedded Multi-Die Interconnect Bridge) Information L-Tile/ H-Tile Building Blocks on page 16 AN778 - Intel Stratix 10 Transceiver Usage for more information about transceiverchannel placement guidelines for both L- and H-Tiles.(1)Refer to the L-Tile/ H-Tile Building Blocks section for further descriptions of GX and | FeedbackIntel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice.

9 Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of :2015 Registered Intel Stratix 10 GX/SX Device Overview for more information about transceivercounts in the various device and tile variants. Intel FPGA IP for Transceiver PHY Support L-Tile/ H-Tile Layout in Intel Stratix 10 Device VariantsIntel Stratix 10 GX/SX device variants support both L- and H-Tiles. Intel Stratix 10 TXand MX device variants support both H- and E-Tiles. Packages that support L-Tile onlyand H-Tile only also support pin Stratix 10 devices are offered in a number of different configurations based onlayout.

10 There is a maximum of six possible locations for a tile. The following figuremaps these layouts to the corresponding Transceiver tiles and Stratix 10 Tile LayoutHSSI_2_1 Tile 1K-NHSSI_2_0 Package SubstrateEMIBEMIBEMIBEMIBCore Fabric Channel543210543210543210543210 Bank1N1M1L1 KEMIBTile 4K-NEMIBTile 4G-JHSSI_1_1 Tile 4C-FHSSI_0_1 Tile 1C-FHSSI_0_0 Tile Intel Stratix 10 GX/SX H-Tile ConfigurationsThe Intel Stratix 10 GX FPGAs meet the high-performance demands of high-throughput systems with up to 10 teraflops (TFLOPS) of floating-point Stratix 10 GX FPGAs also provide Transceiver support up to Gbps for chip-module, chip-to-chip, and backplane Intel Stratix 10 SX SoCs features a hard processor system with 64 bit quad-coreARM* Cortex*-A53 processor available in all densities, in addition to all the features ofIntel Stratix 10 GX OverviewUG-20055 | Stratix 10 L- and H-Tile Transceiver PHY User GuideSend Feedback8 Figure Stratix 10 GX/SX Device with 1 H-Tile (24 Transceiver Channels)L-Tile/ H-Tile (24 Channels)HSSI_0_0 Package SubstrateEMIBCore Fabric GX/SX 400 HF35 (F1152)GX/SX 650 HF35 (F1152)GX/SX 2500 HF55 (F2912A)GX/SX 2800 HF55 (F2912A)GX/SX 4500 HF55 (F2912A)GX/SX 5500 HF55 (F2912A)Figure Stratix 10 GX/SX Device with 2 H-Tiles (48 Transceiver Channels)L-Tile/ H-Tile (24 Channels)HSSI_2_0L-Tile/ H-Tile (24 Channels)HSSI_0_0 Package SubstrateEMIBEMIBCore Fabric GX/SX 850 NF43 (F1760A)